Verilog testbench的写法之输入输出文件

以下为代码和解释：

`timescale 1ns / 1ps


// Company: 
// Engineer:
//
// Create Date:   15:03:48 08/31/2016
// Design Name:   Gaussian1
// Module Name:   D:/SIFT/project/SIFT_Gaussian/tb_Gaussian1.v
// Project Name:  SIFT_Gaussian
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Gaussian1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module tb_Gaussian1;

	// Inputs
	reg CLK;
	reg nRESET;
	reg [7:0] PIXEL_IN;
	reg VALID_IN;

	// Outputs
	wire VALID_OUT;
	wire [1214:0] DATA_OUT;
	
	reg [7:0] image_b [0:1023];  //输入文件大小
	integer read_addr;
	
	integer read_image_point;
	integer image_point;
	
	integer i;
	
	reg [14:0]data_buffer[0:575][0:80]  //输出文件大小
	integer data_cnt;
	integer data_cnt2;
	
	reg [18:0] write_addr;
	integer write_text_point;

	// Instantiate the Unit Under Test (UUT)
	Gaussian1 uut (
		.CLK