设计要求
设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。给出HDL设计及testbench描述,综合后的时序仿真结果及分析说明。
提示
系统化分为状态机控制器和数据通路,信号的接口关系可参考下图(a)所示:
数据通路包括一个位计数器(k)、一个存储寄存器(tmp)、一个间隙寄存器(Gap)。
控制器产生的控制信号包括:
flush_tmp:清空tmp寄存器
incr_tmp: 增加tmp寄存器
store_tmp:用tmp加载Gap
incr_k: 增加k计数器
系统的参考ASMD图如图(b)所示:
设计代码:
module Gap_finder(
input clk,
input rst,
input [31:0] data_in,
output [5:0] gap
);
reg [5:0] tmp,k,gap;
reg flush_tmp,store_tmp,incr_k,incr_tmp;
parameter s_0=0,s_1=1,s_2=2,s_done=3;
reg[1:0] state,next_state;
wire Bit=data_in[k];
always @(posedge clk,posedge rst)
if(rst)
state<=s_0;
else
state<=next_state;
always @(state or Bit or k)
begin
next_state=state;
incr_tmp=0;
incr_k=0;
store_tmp=0;
flush_tmp=0;
case(state)
s_0:
if(k==31)
next_state=s_done;
else
if(!Bit) begin
next_state=s_1;
incr_k=1;
end
else begin
next_state=s_0;
incr_k=1;
end
s_1:
if(k==31)
next_state=s_done;
else if(Bit)
begin
next_state=s_2;
incr_k=1;
incr_tmp=1;
end
else begin
next_state=s_1;
incr_k=1;
end
s_2 :
if(k==31)
if(!Bit)
if(tmp>gap)begin
store_tmp=1;
next_state=s_done;
end
else begin
next_state=s_done;
end
else begin
next_state=s_done;
end
else begin
if(!Bit)
if(tmp>gap)begin
store_tmp=1;
next_state=s_1;
incr_k=1;
flush_tmp=1;
end
else begin
flush_tmp=1;
incr_k=1;
end
else begin
incr_tmp=1;
incr_k=1;
next_state=s_2;
end
end
s_done :
begin
next_state=s_0;
incr_k=0;
end
default :
next_state=s_0;
endcase
end
always @(posedge clk,posedge rst)
begin
if(rst)begin
k<=0;
tmp<=0;
gap<=0;
end
else begin
if(flush_tmp)
tmp<=0;
if(store_tmp)
gap<=tmp;
if(incr_k)
k<=k+1;
if(incr_tmp)
tmp<=tmp+1;
end
end
endmodule
测试代码:
module test();
// Inputs
reg clk;
reg rst;
reg [31:0] data_in;
// Outputs
wire [5:0] gap;
// Instantiate the Unit Under Test (UUT)
Gap_finder uut (
.clk(clk),
.rst(rst),
.data_in(data_in),
.gap(gap)
);
always #5 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
data_in = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
data_in =32'hffff_7fea; //gap=0x0a
end
endmodule
仿真图
实例1:
data_in =32’hffff_7fea=32’h 1111_1111_1111_1111_0111_1111_1110_101;
run post-implementation timing simulation 运行实现后时序仿真(最接近真实的仿真结果)
最后得出gap=0x0a,结果正确。在gap从01往0a跳变时,出现毛刺
实例2:
data_in = 32’h7fff_fffe=32’h0111_1111_1111_1111_1111_1111_1111_1110
时序仿真:
最后得出gap=0x1e=30,结果正确。在gap从00往1e跳变时,出现毛刺