HDLBits记录（五）

记录在HDLBits上做的题目,如有错误，欢迎指正。
HDLBits记录(一): 1 Getting Started and 2 Verilog Language.
HDLBits记录(二): 3 Circuits / 3.1 Combinational Logic.
HDLBits记录(三): 3 Circuits / 3.2 Sequential Logic.
HDLBits记录(四): 3 Circuits / 3.3 Building Larger Circuits.
HDLBits记录(五): 4 Verification: Reading Simulations and 5 Verification: Writing Testbenches.

---

4 Verification: Reading Simulations

4.1 Finding bugs in code

1 Mux

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0]out  );

    assign out = ({8{sel}} & a) | (~{8{sel}} & b);

endmodule

2 NAND

module top_module (input a, input b, input c, output out);//
    wire temp;
    andgate inst1 ( temp, a, b, c, 1'b1,1'b1 );
    assign out = ~temp;
endmodule

3 Mux

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] mux0, mux1;
    mux2 mux_0 ( sel[0],    a,    b, mux0 );
    mux2 mux_1 ( sel[0],    c,    d, mux1 );
    mux2 mux_2 ( sel[1], mux0, mux1,  out );

endmodule

4 Add/sub

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (~(|out))
            result_is_zero = 1;
        else 
            result_is_zero = 0;
    end

endmodule

5 Case statement

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 
);//

     always @(*)
        case (code)
            8'h45: begin out = 0; valid = 1; end
            8'h16: begin out = 1; valid = 1; end
            8'h1e: begin out = 2; valid = 1; end
            8'h26: begin out = 3; valid = 1; end
            8'h25: begin out = 4; valid = 1; end
            8'h2e: begin out = 5; valid = 1; end
            8'h36: begin out = 6; valid = 1; end
            8'h3d: begin out = 7; valid = 1; end
            8'h3e: begin out = 8; valid = 1; end
            8'h46: begin out = 9; valid = 1; end
            default: begin out = 0; valid = 0;end
        endcase

endmodule

4.2 Build a circuit from a simulation waveform

1 Combinational circuit 1

module top_module (
    input a,
    input b,
    output q );//

    assign q = a&b; // Fix me

endmodule

2 Combinational circuit 2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = ((a+b+c+d) == 2) | ((a+b+c+d) == 0) | ((a+b+c+d) == 4); // Fix me

endmodule

3 Combinational circuit 3

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = (a&c) | (a&d) | (b&c) | (b&d); // Fix me

endmodule

4 Combinational circuit 4

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b|c; // Fix me

endmodule

5 Combinational circuit 5

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );

    
    always @(*)begin
        case(c)
            4'd0 : q = b;
            4'd1 : q = e;
            4'd2 : q = a;
            4'd3 : q = d;
            default : q = 4'hf;
        endcase
    end
endmodule

6 Combinational circuit 6

module top_module (
    input [2:0] a,
    output [15:0] q ); 
    
    always @(*)begin
        case(a)
            3'b000: q = 16'h1232;
			3'b001: q = 16'haee0;
			3'b010: q = 16'h27d4;
			3'b011: q = 16'h5a0e;
			3'b100: q = 16'h2066;
			3'b101: q = 16'h64ce;
			3'b110: q = 16'hc526;
			3'b111: q = 16'h2f19;
        endcase
    end

endmodule

7 Sequential circuit 7

module top_module (
    input clk,
    input a,
    output q );

    always @(posedge clk)begin
       q <= ~a; 
    end
endmodule

8 Sequential circuit 8

module top_module (
    input clock,
    input a,
    output reg p,
    output reg q );

    always @(*)begin
        if(clock)
            p <= a;
    end
            
    always @(negedge clock)
        q <= a;
endmodule

9 Sequential circuit 9

module top_module (
    input clk,
    input a,
    output [3:0] q );
    always @(posedge clk)
        if(a)
            q <= 4'd4;
    	else if(q == 4'd6)
        	q<=0;
    	else
            q <= q + 1'b1;
endmodule

10 Sequential circuit 10

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );

    always @(posedge clk)begin
        if(a==b)
            state <= a;
    end
    
    assign q = (a==b) ? state : ~state;
    
endmodule

5 Verification: Writing Testbenches

1 clock

module top_module ( );
    reg clk;
    initial clk = 0;
    always #5 clk = ~clk; 
    dut dut_0(clk);
endmodule

2 Testbench1

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
		A = 0; B = 0;
    	#10 A = 1;
        #5 B = 1;
        #5 A = 0;
        #20 B = 0;
    end

endmodule

3 AND gate

module top_module();

    reg [1:0] in;
    wire out;
    
    initial in = 2'd00;
    initial #20 in[1] = 1;
    initial begin
        #10 in[0] = 1;
        #10 in[0] = 0;
        #10 in[0] = 1;
    end
    andgate u0(in, out);
    
endmodule

4 Testbench2

module top_module();

    reg clk;
    reg in;
    reg [2:0] s;
    
    wire out;
    
    always #5 clk = ~clk; 
    initial begin
    	clk = 0;
        in = 0;
        s = 3'd2;
        #10 s = 3'd6;
        #10 s = 3'd2; in = 1;
        #10 s = 3'd7; in = 0;
        #10 s = 3'd0; in = 1;
        #30 in = 0;
    end
   
    
    q7 u0(clk, in, s, out);
endmodule

5 T flip-flop

module top_module ();

    reg clk, reset, t;
    wire q;
    
    always #5 clk = ~clk;
    initial begin 
    	clk = 0;
        reset =0;
        t = 0;
        #10 reset = 1;
        #10 reset = 0; t = 1;
    end
    tff u0( clk, reset, t,q);
endmodule