HDLBits记录（三）

最新推荐文章于 2023-09-19 22:11:24 发布
最新推荐文章于 2023-09-19 22:11:24 发布
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分类专栏： # verilog学习 文章标签： verilog
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本文链接：https://blog.csdn.net/sinat_39901027/article/details/107669262
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记录在HDLBits上做的题目,如有错误，欢迎指正。
HDLBits记录(一): 1 Getting Started and 2 Verilog Language.
HDLBits记录(二): 3 Circuits / 3.1 Combinational Logic.
HDLBits记录(三): 3 Circuits / 3.2 Sequential Logic.
HDLBits记录(四): 3 Circuits / 3.3 Building Larger Circuits.
HDLBits记录(五): 4 Verification: Reading Simulations and 5 Verification: Writing Testbenches.

目录

3 Circuits

3.2 sequential Logic

3.2.1 latches and Flip-Flops

1 DFF

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
    always @(posedge clk) begin
        q <= d;
    end
endmodule

2 DFF

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q);

    always @(posedge clk) begin
    	q <= d;
    end

endmodule

3 DFF with reset

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk) begin
        if(reset)
            q <= 0;
        else
        	q <= d;
    end

endmodule

4 DFF with reset value

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q );
    always @(negedge clk) begin
        if(reset)
            q <= 8'h34;
        else
        	q <= d;
    end
endmodule

5 DFF with asynchronous reset

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset) begin
        if(areset)
            q <= 0;
        else
        	q <= d;
    end
endmodule

6 DFF with byte enable

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always @(posedge clk)begin
        if(!resetn)
            q <= 0;
        else begin
            if(byteena[1])
               q[15:8] <= d[15:8]; 
        	else
               q[15:8] <= q[15:8];
            
            if(byteena[0])
                q[7:0] <= d[7:0];
            else
                q[7:0] <= q[7:0];
        end
    end
endmodule

7 D latch

module top_module (
    input d, 
    input ena,
    output q);
	assign q = ena ? d : q;
endmodule

8 DFF

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always @(posedge clk or posedge ar)begin
        if(ar)
            q <= 0;
        else
            q <= d;
    end
endmodule

9 DFF

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always @(posedge clk)begin
        if(r)
            q <= 0;
        else
            q <= d;
    end
endmodule

10 DFF+gate

module top_module (
    input clk,
    input in, 
    output out);
    always @(posedge clk)begin
    	out <= in ^ out;
    end
endmodule

11 mux and DFF

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);

    always @(posedge clk) begin
        if(L)
            Q <= r_in;
    	else
            Q <= q_in;
    end
        
endmodule

12 mux and DFF

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    always @(posedge clk) begin
        if(L)
            Q <= R;
        else
            if(E)
                Q <= w;
        	else
                Q <= Q;
    end
endmodule

13 DFFs and gate

module top_module (
    input clk,
    input x,
    output z
); 
    reg [2:0] q = 3'b0;
    
    always @(posedge clk)begin
        q[0] <= x ^ q[0];
        q[1] <= x & ~q[1];
        q[2] <= x | ~q[2];
    end
    
    assign z = ~(q[0] | q[1] | q[2]);
    
endmodule

14 creat circuit from truth table (JK)

module top_module (
    input clk,
    input j,
    input k,
    output Q); 

    always @(posedge clk) begin
        case({j,k})
            2'b00: Q <= Q;
            2'b01: Q <= 0;
            2'b10: Q <= 1;
            2'b11: Q <= ~Q;            
        endcase        
    end
endmodule

15 detect an edge

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] in_reg;
    always @(posedge clk)begin
       in_reg <= in;
        pedge <= ~in_reg & in;
    end

endmodule

16 detect both edge

17 edge capture register

18 dual-edge triggered flip-flop

module top_module (
    input clk,
    input d,
    output q
);
    reg q1,q2;
    
    always @(posedge clk)begin
        q1 <= d;
    end
    always @(negedge clk)begin
        q2 <= d;
	end
    
    assign q = clk ? q1 : q2;
    
endmodule
3.2.2 counters

1 foub-bit binary counter

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);

    always @(posedge clk)begin
        if(reset)
            q <= 3'b0;
        else
            q <= q + 1'b1;
    end
    
endmodule

2 decade counter

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    
    always @(posedge clk)begin
        if(reset)
            q <= 3'b0;
        else
            if(q == 4'd9)
                q <= 0;
        	else
            	q <= q + 1'b1;
    end
endmodule

3 decade counter again

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    
    always @(posedge clk)begin
        if(reset)
            q <= 4'b1;
        else
            if(q == 4'd10)
                q <= 1;
        	else
            	q <= q + 1'b1;
    end

endmodule

4 slow decade counter

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    
    always @(posedge clk)begin
        if(reset)
            q <= 4'b0;
        else
            if (slowena)
            	if(q == 4'd9)
                	q <= 0;
        		else
            		q <= q + 1'b1;
        	else 
                q <= q;
    end
endmodule

5 counter 1-12

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d  ); 
    
	assign c_enable = enable;
    assign c_load = reset | (Q == 4'd12 & enable);
    assign c_d = 4'd1;
    
    count4 the_counter (.clk(clk), .enable(c_enable), .load(c_load), .d(c_d), .Q(Q));

endmodule

13 counter 100

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    wire [3:0] q1,q2,q3;
    
    assign c_enable[0] = 1'b1;
    assign c_enable[1] = (q1 == 4'd9);
    assign c_enable[2] = (q1 == 4'd9 & q2 == 4'd9);
    assign OneHertz = (q1 == 4'd9 & q2 == 4'd9 & q3 == 4'd9); 
    
    bcdcount counter0 (clk, reset, c_enable[0], q1);
    bcdcount counter1 (clk, reset, c_enable[1], q2);
    bcdcount counter2 (clk, reset, c_enable[2], q3);
    
endmodule

14 4- digit decimal counter

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
	
	always @(posedge clk) begin
		if (reset) begin
			ena <= 3'b0;
		end
		else begin
			if (q[3:0] == 4'd8 ) begin
				ena[1] <= 1;
			end
			else
				ena[1] <= 0;

			if (q[7:4] == 4'd9 && q[3:0] == 4'd8) begin
				ena[2] <= 1;
			end
			else
				ena[2] <= 0;

			if (q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd8) begin
				ena[3] <= 1;
			end
			else
				ena[3] <= 0;		
		end
	end

	always @(posedge clk) begin
		if (reset) begin
			q <= 16'b0;
		end
		else begin
			if (ena[1]) begin
				q[3:0] <= 4'b0;
				q[7:4] <= q[7:4] + 1'b1;
			end
			else begin
				q[3:0] <= q[3:0] + 1'b1;
				q[7:4] <= q[7:4];				
			end

			if (ena[2]) begin
				q[7:4] <= 4'b0;
				q[11:8] <= q[11:8] + 1'b1;
			end
			else
				q[11:8] <= q[11:8];

			if (ena[3]) begin
				q[11:8] <= 4'b0;
				
				if (q[15:12] == 4'd9 )
			    	q[15:12] <= 4'b0;
				else
					q[15:12] <= q[15:12] + 1'b1;
			end
			else
				q[15:12] <= q[15:12];	
		end
	end
endmodule

15 12-hour clock

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    //例化计数器表示秒
    wire ssl_2_ssh,ssh_2_mml;   //地位向高位进位
    cnt cnt_ssl(.clk(clk),.reset(reset),.count_start(ena),.count_end(4'd9),.end_cnt(ssl_2_ssh),.count(ss[3:0]));
    cnt cnt_ssh(.clk(clk),.reset(reset),.count_start(ssl_2_ssh),.count_end(4'd5),.end_cnt(ssh_2_mml),.count(ss[7:4]));
   
    //例化计数器表示分钟
    wire mml_2_mmh, mmh_2_hh;
    cnt cnt_mml(.clk(clk),.reset(reset),.count_start(ssh_2_mml),.count_end(4'd9),.end_cnt(mml_2_mmh),.count(mm[3:0]));
    cnt cnt_mmh(.clk(clk),.reset(reset),.count_start(mml_2_mmh),.count_end(4'd5),.end_cnt(mmh_2_hh),.count(mm[7:4]));
    
    //小时计数
    reg a_2_p;
    always @(posedge clk)begin
        if(reset)begin
            a_2_p <= 0;
            hh <= 8'h12;        // 初始条件 12:00:00 AM
        end
        else if(mmh_2_hh)begin
            if(hh == 8'h12)
                hh <= 8'h01;
            else begin
                hh <= hh + 1'b1;
                if(hh == 8'h09)
                    hh <= 8'h10;
                if(hh == 8'h11)
                    a_2_p <= ~ a_2_p;
            end
        end
    end
    assign pm = a_2_p;
endmodule

//计数器子模块，可以设置开始和结束条件
module cnt(
    input clk,
    input reset,
    input count_start,     //开始计数输入
    input [3:0] count_end, //计数到多少停止计数
    output end_cnt,        //一次计数完成标志
    output [3:0] count);
 
    wire add_cnt;
    always @(posedge clk)begin
        if(reset)begin
           count <= 4'd0; 
        end
        else if(add_cnt)begin
            if(end_cnt)
                count <= 4'd0;
            else
                count <= count + 1'b1;
        end
    end
    assign add_cnt = count_start;   //计数开始条件，当满足了开始计数
    assign end_cnt = add_cnt && count == count_end;    //计数结束产生一个标志
endmodule
3.2.3 shift registers

1 4-bit shift registers

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
	
	always @(posedge clk or posedge areset) begin
		if (areset) begin
			q <= 4'b0;			
		end
		else begin
			if (load) begin
			 	q <= data;
			end
			else if (ena) begin
				q <= q >> 1;
			end	
			else 
				q <= q;		
		end
	end
endmodule

2 left/rignt rotator


module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
	integer i;
	
	always @(posedge clk) begin
		if (load) begin
			q <= data;
		end
		else if (ena == 2'b01) begin
			q[99] <= q[0];
			for (i = 0; i <= 98; i = i + 1)
			    q[i] <= q[i+1];
		end
		else if (ena == 2'b10) begin
			q[0] <= q[99];
			for (i = 1; i <= 99; i = i + 1)
			    q[i] <= q[i-1];
		end
		else
			q <= q;
	end
endmodule

3 left/rignt arthmetic shift by 1 or 8

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
	
	always @(posedge clk) begin
		if (load) begin
			q <= data;
		end
		else if (ena) begin
			case (amount) 
			    2'b00: q <= q <<< 1;
			    2'b01: q <= q <<< 8;
			    2'b10: q <= {{q[63]},{q[63:1]}};
                2'b11: q <= {{8{q[63]}},{q[63:8]}};			            
			endcase
		end
		else
			q <= q;
	end
endmodule

4 5-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
	always @ (posedge clk) begin
		if (reset) begin
			q <= 4'b1;        
		end
		else begin
		   q[4] <= q[0] ^ 1'b0;
		   q[3] <= q[4]       ;
		   q[2] <= q[3] ^ q[0];
		   q[1] <= q[2] 	  ;
           q[0] <= q[1]       ;
	    end
	end
endmodule

5 3-bit LFSR

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
	
	always @(posedge KEY[0]) begin
		LEDR[0] <= KEY[1] ? SW[0] : LEDR[2];
		LEDR[1] <= KEY[1] ? SW[1] : LEDR[0];
		LEDR[2] <= KEY[1] ? SW[2] : (LEDR[1] ^ LEDR[2]);
	end

endmodule

6 32-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q ); 
	
	always @ (posedge clk) begin
		if(reset)
			q <= 32'h1;
		else begin
	        q <= {q[0], q[31:1]};
	        q[31] <= q[0] ^ 1'b0; 
            q[21] <= q[0] ^ q[22];
	        q[1]  <= q[0] ^ q[2];
	        q[0]  <= q[0] ^ q[1];
        end
	end
endmodule

7 shift register

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
	
	reg q_0,q_1,q_2;
	always @(posedge clk) begin
		if (!resetn) begin
			q_0 <= 0;
			q_1 <= 0;
			q_2 <= 0;
			out <= 0;	
		end
		else begin
			q_0 <= in;
			q_1 <= q_0;
			q_2 <= q_1;
			out <= q_2;				
		end
	end
endmodule

8 shift register

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF u_1(.clk(KEY[0]), .w(KEY[3]), .E(KEY[1]), .R(SW[3]), .L(KEY[2]), .q(LEDR[3]));
    MUXDFF u_2(.clk(KEY[0]), .w(LEDR[3]), .E(KEY[1]), .R(SW[2]), .L(KEY[2]), .q(LEDR[2]));
    MUXDFF u_3(.clk(KEY[0]), .w(LEDR[2]), .E(KEY[1]), .R(SW[1]), .L(KEY[2]), .q(LEDR[1]));
    MUXDFF u_4(.clk(KEY[0]), .w(LEDR[1]), .E(KEY[1]), .R(SW[0]), .L(KEY[2]), .q(LEDR[0]));
endmodule

module MUXDFF (
	input clk,
	input w,
	input E,
	input R,
	input L,
	output q
	);
	always @(posedge clk) begin
		q <= L ? R : (E ? w : q);
	end
endmodule

9 3-input LUT

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 

	reg [7:0] q;

	always @(posedge clk) begin
		if (enable) begin
		    q <= {q[6:0], S};   
		end
		else 
			q <= q;
	end

	always @(*) begin
		case ({A,B,C}) 
		    3'b000: Z <= q[0];
		    3'b001: Z <= q[1];
		    3'b010: Z <= q[2];
		    3'b011: Z <= q[3];
		    3'b100: Z <= q[4];
		    3'b101: Z <= q[5];
		    3'b110: Z <= q[6];
		    3'b111: Z <= q[7];
		endcase
	end
endmodule
3.2.4 More Circuits

1 Rule 90

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    integer i;
    always @(posedge clk)begin
        if(load)begin
           q <= data; 
        end
        else begin
            q[0] <= 1'b0 ^ q[1];
            q[511] <= 1'b0 ^ q[510];
            for(i = 1; i < 511; i = i + 1)begin
                q[i] <= q[i-1] ^ q[i+1]; 
            end
        end
    end
endmodule

2 Rule 110

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    integer i;
    always @(posedge clk)begin
        if(load)begin
           q <= data; 
        end
        else begin
            q[0] <= q[0];
            q[511] <= q[511] | q[510];
            for(i = 1; i < 511; i = i + 1)begin
                q[i] <= (~q[i+1] & (q[i] | q[i-1])) |  (q[i+1] & (q[i] ^ q[i-1])); 
            end
        end
    end
endmodule

3 Conway’s Game of Life 16x16
3.2.5 Finite State Machines

1 simple FSM 1

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=1'b0, B=1'b1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        if (state == B) 
        	next_state = in ? B : A;
        else if(state == A) 
        	next_state = in ? A : B;
        else 
            next_state = next_state;
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if (areset) begin
        	state <= B;        
        end
        else begin
        	state <= next_state;        
        end
    end

    // Output logic
    assign out = (state == B);

endmodule

2 simple FSM 1.2

module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A=1'b0, B=1'b1; 
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            present_state = B;
        end 
        else begin
            case (present_state)
                B : if (in == 1'b0) 
                        next_state = A;
                	else 
                		next_state = present_state;
                A : if (in == 1'b0) 
                        next_state = B;
                	else 
                		next_state = present_state;
            endcase

            // State flip-flops
            present_state = next_state;   
		end
            case (present_state)
                // Fill in output logic
                B : out = 1;
                A : out = 0;
            endcase
       
    end

endmodule

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    wire out;

    // Fill in state name declarations
	parameter A=1'b0;
    parameter B=1'b1;

    reg state;
    
	assign out = state;
    
    always @(posedge clk) begin
        if (reset) begin  
            state = B;
        end else begin
            case (state)
                A: begin state = (in==0)?B:A; end
                B: begin state = (in==0)?A:B; end
            endcase
        end
    end

endmodule

3 simple FSM 2

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        if(state == OFF) begin
            next_state = (j==1) ? ON : OFF;
        end
        else if(state == ON) begin
            next_state = (k==1) ? OFF : ON;
        end
        else
            next_state = OFF;
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset) begin
            state <= OFF;
        end
        else begin
            state <= next_state;
        end 
    end

    // Output logic
    assign out = (state == ON);

endmodule

4 simple FSM 2

module top_module(
    input clk,
    input reset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        if(state == OFF) begin
            next_state = (j==1) ? ON : OFF;
        end
        else if(state == ON) begin
            next_state = (k==1) ? OFF : ON;
        end
        else
            next_state = OFF;
    end

    always @(posedge clk) begin
        // State flip-flops with asynchronous reset
        if(reset) begin
            state <= OFF;
        end
        else begin
            state <= next_state;
        end 
    end

    // Output logic
    assign out = (state == ON);

endmodule

5 Simple state transitions 3

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: next_state = f(state, in)
    always @(*) begin
        case(state)
            A : begin next_state = in ? B: A; end
            B : begin next_state = in ? B: C; end
            C : begin next_state = in ? D: A; end
            D : begin next_state = in ? B: C; end
        endcase
    end
    // Output logic:  out = f(state) for a Moore state machine
    assign out = (state == D);
endmodule

6 Simple one-hot state transitions 3

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A] & ~in) | (state[C] & ~in);
    assign next_state[B] = (state[A] &  in) | (state[B] &  in) | (state[D] &  in);
    assign next_state[C] = (state[B] & ~in) | (state[D] & ~in);
    assign next_state[D] = (state[C] &  in) ;

    // Output logic: 
    assign out = (state[D] == 1);

endmodule

7 Simple FSM3 (asynchronous reset)

module top_module(
    input clk,
    input in,
    input areset, 
    output out); 

    reg [3:0] state, next_state;

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A] & ~in) | (state[C] & ~in);
    assign next_state[B] = (state[A] &  in) | (state[B] &  in) | (state[D] &  in);
    assign next_state[C] = (state[B] & ~in) | (state[D] & ~in);
    assign next_state[D] = (state[C] &  in) ;

    always @(posedge clk or posedge areset) begin
        if(areset) begin
            state <= 4'b0001;
        end
        else begin
            state <= next_state;
        end 
    end

    // Output logic
    assign out = (state == 4'b1000);

endmodule

8 Simple FSM3 (synchronous reset)

module top_module(
    input clk,
    input in,
    input reset,    
    output out);

    reg [3:0] state, next_state;

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A] & ~in) | (state[C] & ~in);
    assign next_state[B] = (state[A] &  in) | (state[B] &  in) | (state[D] &  in);
    assign next_state[C] = (state[B] & ~in) | (state[D] & ~in);
    assign next_state[D] = (state[C] &  in) ;

    always @(posedge clk) begin
        if(reset) begin
            state <= 4'b0001;
        end
        else begin
            state <= next_state;
        end 
    end

    // Output logic
    assign out = (state == 4'b1000);

endmodule

9 Design a Moore FSM

10 Lemmings1

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin
        if(state == LEFT)begin
            if(bump_left)begin 
               next_state = RIGHT; 
            end
            else begin
                next_state = LEFT; 
            end
        end
        else begin
            if(bump_right)begin 
               next_state = LEFT; 
            end
            else begin
               next_state = RIGHT; 
            end
        end
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin
           state <= LEFT; 
        end
        else begin
           state <= next_state; 
        end
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);

endmodule

11 Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    parameter LEFT=0, RIGHT=1, FALL_L = 2, FALL_R = 3; 
    reg [1:0] state, next_state;
    
    always @(*) begin
        case(state)
            LEFT : begin
                if(~ground) begin
                   next_state = FALL_L;
                end
                else if(bump_left)begin 
               		next_state = RIGHT; 
            	end
            	else begin
                	next_state = LEFT; 
            	end 
            end
            RIGHT : begin 
                if(~ground) begin
                   next_state = FALL_R;  
                end
                else if(bump_right)begin 
               		next_state = LEFT; 
            	end
            	else begin
                	next_state = RIGHT; 
            	end 
            end
            FALL_L : begin 
                if(~ground) begin
                   next_state = FALL_L;  
                end
            	else begin
                	next_state = LEFT; 
            	end 
            end
            FALL_R : begin 
                if(~ground) begin
                   next_state = FALL_R;  
                end
            	else begin
                	next_state = RIGHT; 
            	end 
            end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin
           state <= LEFT; 
        end
        else begin
           state <= next_state; 
        end
    end

    // Output logic
    assign walk_left  = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah       = (state == FALL_R | state == FALL_L);
endmodule

12 Lemmings 3

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    parameter LEFT=0, RIGHT=1, FALL_L = 2, FALL_R = 3, DIG_L = 4, DIG_R = 5; 
    reg [2:0] state, next_state;
    
    always @(*) begin
        case(state)
            LEFT : begin
                if(~ground) begin
                   next_state = FALL_L;
                end
                else if(dig) begin
                    next_state = DIG_L; 
                end
                else if(bump_left)begin 
               		next_state = RIGHT; 
            	end
            	else begin
                	next_state = LEFT; 
            	end 
            end
            RIGHT : begin 
                if(~ground) begin
                   next_state = FALL_R;  
                end
                else if(dig) begin
                    next_state = DIG_R; 
                end
                else if(bump_right)begin 
               		next_state = LEFT; 
            	end
            	else begin
                	next_state = RIGHT; 
            	end 
            end
            FALL_L : begin 
                if(~ground) begin
                   next_state = FALL_L;  
                end
            	else begin
                	next_state = LEFT; 
            	end 
            end
            FALL_R : begin 
                if(~ground) begin
                   next_state = FALL_R;  
                end
            	else begin
                	next_state = RIGHT; 
            	end 
            end
            DIG_L : begin
                if(~ground) begin
                   next_state = FALL_L;  
                end
            	else begin
                	next_state = DIG_L; 
            	end 
            end
            DIG_R : begin
                if(~ground) begin
                   next_state = FALL_R;  
                end
            	else begin
                	next_state = DIG_R; 
            	end 
            end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin
           state <= LEFT; 
        end
        else begin
           state <= next_state; 
        end
    end

    // Output logic
    assign walk_left  = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah       = (state == FALL_R | state == FALL_L);
    assign digging    = (state == DIG_R  | state == DIG_L);
endmodule

13 Lemmings4

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    parameter LEFT=0, RIGHT=1, FALL_L = 2, FALL_R = 3, DIG_L = 4, DIG_R = 5, SPLAT = 6; 
    reg [2:0] state, next_state;
    reg [4:0] time_cnt;
    
    always @(*) begin
        case(state)
            LEFT : begin
                if(~ground) begin
                   next_state = FALL_L;
                end
                else if(dig) begin
                    next_state = DIG_L; 
                end
                else if(bump_left)begin 
               		next_state = RIGHT; 
            	end
            	else begin
                	next_state = LEFT; 
            	end 
            end
            RIGHT : begin 
                if(~ground) begin
                   next_state = FALL_R;  
                end
                else if(dig) begin
                    next_state = DIG_R; 
                end
                else if(bump_right)begin 
               		next_state = LEFT; 
            	end
            	else begin
                	next_state = RIGHT; 
            	end 
            end
            FALL_L : begin 
                if(~ground) begin
                   next_state = FALL_L;  
                end
                else if(time_cnt > 20) begin
                    next_state = SPLAT; 
                end
            	else begin
                	next_state = LEFT; 
            	end 
            end
            FALL_R : begin 
                if(~ground) begin
                   next_state = FALL_R;  
                end
                else if(time_cnt > 20) begin
                    next_state = SPLAT; 
                end
            	else begin
                	next_state = RIGHT; 
            	end 
            end
            DIG_L : begin
                if(~ground) begin
                   next_state = FALL_L;  
                end
                
            	else begin
                	next_state = DIG_L; 
            	end 
            end
            DIG_R : begin
                if(~ground) begin
                   next_state = FALL_R;  
                end
            	else begin
                	next_state = DIG_R; 
            	end 
            end
            SPLAT : begin
                next_state = SPLAT;  
            end
        endcase
    end

    always @(posedge clk or posedge areset) begin
        if(areset)begin
           time_cnt <= 0; 
        end
        else if(~ground)begin
            time_cnt <= time_cnt + 1'b1;
        end
        else begin
            time_cnt <= 0; 
        end 
    end
    
    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin
           state <= LEFT; 
        end
        else begin
           state <= next_state; 
        end
    end

    // Output logic
    assign walk_left  = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah       = (state == FALL_R | state == FALL_L);
    assign digging    = (state == DIG_R  | state == DIG_L);
endmodule

14 one-hot FSM

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);

    assign next_state[0] = (state[0] & ~in) | (state[1] & ~in) | (state[2] & ~in) | (state[3] & ~in) | (state[4] & ~in) | (state[7] & ~in) | (state[8] & ~in) | (state[1] & ~in) | (state[9] & ~in);
    assign next_state[1] = (state[0] & in) | (state[8] & in) | (state[9] & in);
    assign next_state[2] = (state[1] & in);
    assign next_state[3] = (state[2] & in);
    assign next_state[4] = (state[3] & in);
    assign next_state[5] = (state[4] & in);
    assign next_state[6] = (state[5] & in);
    assign next_state[7] = (state[6] & in) | (state[7] & in);
    assign next_state[8] = (state[5] & ~in);
    assign next_state[9] = (state[6] & ~in);
     
    assign out1 = state[8] | state[9];
    assign out2 = state[7] | state[9];
endmodule

15 PS/2 packet parser

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter byte1 = 0, byte2 = 1,byte3 = 2, error = 3;
    
    reg[1:0] state, next_state;
    
    
    // State transition logic (combinational)
    always @(*)begin
        case(state)
            byte1 : begin next_state = in[3] ? byte2 : byte1; end
            byte2 : begin next_state = byte3; end
            byte3 : begin next_state = error ; end
            error : begin next_state = in[3] ? byte2 : byte1 ;end
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)begin
            state <= byte1;
        end
        else begin
           state <= next_state;
        end
    end
    // Output logic
    assign done = (state == error);
endmodule

16 PS/2 packet parser and datapath

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2
   parameter byte1 = 0, byte2 = 1,byte3 = 2, error = 3;
    
    reg[1:0] state, next_state;
    
    
    // State transition logic (combinational)
    always @(*)begin
        case(state)
            byte1 : begin next_state = in[3] ? byte2 : byte1; end
            byte2 : begin next_state = byte3; end
            byte3 : begin next_state = error ; end
            error : begin next_state = in[3] ? byte2 : byte1 ;end
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)begin
            state <= byte1;
        end
        else begin
           state <= next_state;
        end
    end
    // Output logic
    assign done = (state == error);
    
    // New: Datapath to store incoming bytes.
    always @(posedge clk)begin
        case(state)
            byte1 : begin out_bytes[23:16] <= in[3] ? in : 8'b0; end
            byte2 : begin out_bytes[15:8] <=  in; end
            byte3 : begin out_bytes[ 7:0] <=  in ; end
            error : begin out_bytes[23:16] <= in[3] ? in : 8'b0;end
        endcase
    end
endmodule

17 serial receiver

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 

    parameter idel = 0, start = 1, bit1=2, bit2=3, bit3=4, bit4=5, bit5=6, bit6=7, bit7=8, bit8=9, stop = 10, error =11;
    reg [3:0] state, next_state;
    
    always @(posedge clk)begin
        if(reset)begin
           state <= idel;
        end
        else begin
           state <= next_state;
        end
    end
    always @(*)begin
        case(state)
            idel:begin next_state = ~in ? start : idel; end
            start:begin next_state = bit1;end
            bit1:begin next_state = bit2;end
            bit2:begin next_state = bit3;end
            bit3:begin next_state = bit4;end
            bit4:begin next_state = bit5;end
            bit5:begin next_state = bit6;end
            bit6:begin next_state = bit7;end
            bit7:begin next_state = bit8;end
            bit8:begin next_state =  in ? stop : error; end
            stop:begin next_state = ~in ? start : idel; end
            error : begin next_state = in ? idel : error; end
        endcase
    end
    
    assign done = (state == stop);
endmodule

18 serial receiver and datapath

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Use FSM from Fsm_serial
    parameter idel = 0, start = 1, bit1=2, bit2=3, bit3=4, bit4=5, bit5=6, bit6=7, bit7=8, bit8=9, stop = 10, error =11;
    reg [3:0] state, next_state;
    
    always @(posedge clk)begin
        if(reset)begin
           state <= idel;
        end
        else begin
           state <= next_state;
        end
    end
    always @(*)begin
        case(state)
            idel:begin next_state = ~in ? start : idel; end
            start:begin next_state = bit1;end
            bit1:begin next_state = bit2;end
            bit2:begin next_state = bit3;end
            bit3:begin next_state = bit4;end
            bit4:begin next_state = bit5;end
            bit5:begin next_state = bit6;end
            bit6:begin next_state = bit7;end
            bit7:begin next_state = bit8;end
            bit8:begin next_state =  in ? stop : error; end
            stop:begin next_state = ~in ? start : idel; end
            error : begin next_state = in ? idel : error; end
        endcase
    end
    
    assign done = (state == stop);
    // New: Datapath to latch input bits.
    always @(posedge clk)begin
        case(state)
            start:begin out_byte[0] <= in;end
            bit1:begin out_byte[1] <= in;end
            bit2:begin out_byte[2] <= in;end
            bit3:begin out_byte[3] <= in;end
            bit4:begin out_byte[4] <= in;end
            bit5:begin out_byte[5] <= in;end
            bit6:begin out_byte[6] <= in;end
            bit7:begin out_byte[7] <= in; end
        endcase
    end
endmodule

19 serial receiver and parity checking

20 sequence recognition

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);

    parameter idel = 0, bit1 = 1, bit2=2, bit3=3, bit4=4, bit5=5, bit6=6,bit7 = 7, s_disc= 8,s_flag = 9,s_error=10;
    reg [3:0] state, next_state;
    
    always @(posedge clk) begin
        if(reset)begin
           state <= idel; 
        end
        else begin 
           state <= next_state; 
        end
    end
    always @(*)begin
        case(state)
            idel : begin next_state = in ? bit1 : idel; end
            bit1: begin next_state = in ? bit2 : idel; end
            bit2: begin next_state = in ? bit3 : idel; end
            bit3: begin next_state = in ? bit4 : idel; end
            bit4: begin next_state = in ? bit6 : idel; end
            bit6: begin next_state = ~in ? s_disc : bit7; end
            bit7: begin next_state = ~in ? s_flag : s_error; end
            s_error: begin next_state = in ? s_error : idel; end
            s_disc : begin next_state = in ? bit1 : idel; end
            s_flag : begin next_state = in ? bit1 : idel; end
        endcase
    end
    
    assign disc = (state == s_disc);
    assign flag = (state == s_flag);
    assign err  = (state == s_error);
endmodule

21 design a Mealy FSM

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    parameter s0 = 0, s1 = 1, s2 = 2;
    reg[1:0] state,next_state;
    
    always @(posedge clk or negedge aresetn)  begin
        if(!aresetn) 
            state <= s0;
        else
            state <= next_state;
    end
    always @(*)begin
        case(state)
            s0: begin next_state =  x ? s1 : s0; end
            s1: begin next_state = ~x ? s2 : s1; end
            s2: begin next_state =  x ? s1 : s0; end
            default : next_state =  s0;
        endcase
    end
    
    assign z = (state == s2 && x == 1);
    
    
endmodule

22 serial two’s complementer (Moore FSM)

23 serial two’s complementer (Mealy FSM)

24 Q3a: FSM

25 Q3b: FSM

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4;
    reg[2:0] state,next_state;
    
    always @(posedge clk)  begin
        if(reset) 
            state <= s0;
        else
            state <= next_state;
    end
    always @(*)begin
        case(state)
            s0: begin next_state =  x ? s1 : s0; end
            s1: begin next_state =  x ? s4 : s1; end
            s2: begin next_state =  x ? s1 : s2; end
            s3: begin next_state =  x ? s2 : s1; end
            s4: begin next_state =  x ? s4 : s3; end
            default : next_state =  s0;
        endcase
    end
    
    assign z = (state == s3 ||state == s4);
endmodule

26 Q3c: FSM logic

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4;
    reg[2:0] next_state;
    
    always @(*)begin
        case(y)
            s0: begin next_state =  x ? s1 : s0; end
            s1: begin next_state =  x ? s4 : s1; end
            s2: begin next_state =  x ? s1 : s2; end
            s3: begin next_state =  x ? s2 : s1; end
            s4: begin next_state =  x ? s4 : s3; end
            default : next_state =  s0;
        endcase
    end
    
    assign Y0 = next_state[0];
    assign z = (y == s3 ||y == s4);
endmodule

27 Q6b: FSM next-state logic

28 Q6c: FSM one-hot next-state logic

29 Q6: FSM

30 Q2a: FSM

31 Q2b: one-hot FSM equations

32 Q2a: FSM

33 Q2b: another FSM
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HDLBits Day10 Edgecapture
山南水北有一方的博客
06-19 2059
这个题是检测下降沿，检测到后out一直为高，知道reset == 1时，out为0。 我自己做：先通过边沿检测，得到一个脉冲信号，然后if这个脉冲信号为高，将其输出给out,输出为低就不管（会保持前面状态）。 但是这样做，边沿检测时会延迟一个clk，在将其输出给out时又会延迟一个clk,这样就与题目中给的时序图不符，看网上答案： module top_module ( input clk, input reset, input [31:0] in, output [31:.
HDLBits刷题全记录（一）
weixin_39677048的博客
10-12 1211
HDLBits刷题记录 ​ HDLBits是一个在线编程网站，可以直接在网站上编辑verilog代码，并进行综合仿真，查看波形图等，非常适合入门学习。 —— HDLBits的官网 ​ 注：可以配合B站的入门视频进行学习 —— Verilog硬件描述语言 西安电子科技大学 蔡觉平等主讲 文章目录HDLBits刷题记录1. Getting StartedGetting StartedOutput Zero2. Verilog LanguageBasicsSimple wireFour wireInverterA
HDLBits刷题全记录（五）
weixin_39677048的博客
10-12 1541
文章目录Finite State MachinesSimple FSM 1_1(asynchronous reset)Simple FSM 1_2(synchronous reset)Simple FSM 2_1(asynchronous reset)Simple FSM 2_2(synchronous reset)Simple state transitions 3Simple one-hot state transitions 3Simple FSM 3_1(asynchronous reset)Sim
HDLBits 错题
qq_36886740的博客
04-10 1434
Count clock - HDLBits 一、信号部分比特位选择 1、 Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should selectin[0], sel=1 selects bitsin[1], sel=2 selects bitsin[2], etc. module top_mo...........
HDLbits中Conwaylife题目解答，以及从中得到关于HLS的一些思考
weixin_45769849的博客
07-28 2864
HDLbits中Conwaylife题目解答，以及从中得到关于HLS的一些思考导言Conwaylife题目的Verilog HDL解答及思路HLS中卷积操作一些思考 导言 笔者最近刚刚刷完HDLbits的所有题目，个人认为其中难度较大的题目，除了状态机的设计外，便是Conwaylife（康威生命游戏），这是一个二维的细胞自动机。这也是为数不多HDLbits中用到for循环语句解答的题，笔者在解题过程中不由得想到了之前利用HLS完成的卷积操作，认为其中有较大的关联性，写下此文用于记录，如果思考有误，也欢迎大家
HDLBits刷题笔记 Edgecapture
weixin_60381535的博客
05-12 191
Verilog源文件。
Verilog刷题HDLBits——Edgecapture
weixin_45968042的博客
12-13 278
【代码】Verilog刷题HDLBits——Edgecapture。
HDLBits 答案之Edgecapture
weixin_43859941的博客
02-23 453
这题还是很巧妙的。首先用了两个always 块，使得输入值在下一个时钟赋给中间值，并且这一操作不会跟Reset always块起冲突。 其次，将检测信号与输出信号相或，得以使输出信号一直维持下去，而不会因为检测信号消失而消失。 module top_module ( input clk, input reset, input [31:0] in, output [31:0] out ); reg [31:0]in1; always @(posedge c.
HDLBits-Edge capture register
qq_40996256的博客
07-10 758
题目： For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset). Each output bit behaves like a SR flip-flop
HDLBits之Dualedge
rosemaryandthyme的博客
02-16 495
巧思时钟上升沿和下降沿都触发时可以使用寄存器 You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge trigge
HDLBits-Dualedge
Royonen的博客
06-10 204
HDLBits-Dualedge
HDLBits学习笔记—— Dualedge
Chika__的博客
05-19 2665
触发器的最后一题，答案解法有点不好理解。 题干： You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge tri
HDLBits：Dualedge双边沿触发
Engineering Lion的博客
09-02 993
verilog无法实现双边沿触发只能单边沿触发，所以我们要实现双边沿触发的方法如下： reg temp,temp1; always @(posedge clk) begin temp <= d ^ temp1; end always @(negedge clk) begin temp1 <= d ^ temp; end assign q = temp ^ temp1; 原理如下： // After posedge
HDLBits学习笔记-Dualedge
weixin_60381535的博客
05-12 139
难点：FPGA中没有双边沿触发器，因此不能在always块中直接使用"posedge clk or negedge clk"的写法。该解法可能会出现毛刺。
HDLBits学习笔记：隐式网络与数组打包技巧
HDLBits学习笔记是一份针对Verilog语言实践者的重要参考资料，特别关注于那些容易导致错误但常被忽视的概念。本文档首先探讨了隐式网络（Implicitnets）在Verilog中的潜在陷阱。在Verilog中，未明确声明的连接或赋值...
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