HDLBits记录（四）

记录在HDLBits上做的题目,如有错误，欢迎指正。
HDLBits记录(一): 1 Getting Started and 2 Verilog Language.
HDLBits记录(二): 3 Circuits / 3.1 Combinational Logic.
HDLBits记录(三): 3 Circuits / 3.2 Sequential Logic.
HDLBits记录(四): 3 Circuits / 3.3 Building Larger Circuits.
HDLBits记录(五): 4 Verification: Reading Simulations and 5 Verification: Writing Testbenches.

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3.3 Building Larger Circuits

1 Counter with period 1000

module top_module (
    input clk,
    input reset,
    output [9:0] q);
	
    always @(posedge clk)begin
        if(reset)
            q <= 0;
        else if(q==10'd999)
            q <= 0;
        else
            q <= q+1;
    end
endmodule

2 4-bit shift register and down counter

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);

    always @(posedge clk)begin
        if (shift_ena)begin
            q[3] <= q[2];
            q[2] <= q[1];
            q[1] <= q[0];
            q[0] <= data;
        end
        if(count_ena)
            q <= q - 1'b1;
    end
endmodule

3 FSM: Sequence 1101 recognizer

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output reg start_shifting
    );
    
    parameter state_1 = 2'b00;
    parameter state_2 = 2'b01;
    parameter state_3 = 2'b10;
    parameter state_4 = 2'b11;

    reg [1:0] state;

    always @(posedge clk) begin
        if(reset)begin
            start_shifting <= 0;
            state <= state_1;
        end
    	else
            case(state)
                state_1: begin if(data == 1'b1) state <= state_2; else state <= state_1; end
                state_2: begin if(data == 1'b1) state <= state_3; else state <= state_1; end
                state_3: begin if(data == 1'b0) state <= state_4; else state <= state_3; end
                state_4: begin if(data == 1'b1) begin state <= state_1; start_shifting <= 1;end else state <= state_1; end
            endcase
    end

endmodule

4 FSM: Enable shift register

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output reg shift_ena);

    reg [2:0] state;
    parameter state_1 = 3'b00;
    parameter state_2 = 3'b01;
    parameter state_3 = 3'b10;
    parameter state_4 = 3'b11;

    always @(posedge clk) begin
        if (reset) begin
            state = state_1;
        end
        case (state)
            state_1 : begin shift_ena <= 1'b1; state <= state_2; end
            state_2 : begin shift_ena <= 1'b1; state <= state_3; end
            state_3 : begin shift_ena <= 1'b1; state <= state_4; end
            state_4 : begin shift_ena <= 1'b1; state <= 3'b111;end
            default : shift_ena <= 1'b0;
        endcase
endmodule

5 FSM:The complete FSM

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    
    parameter s1 = 1, s2 = 2, s3 = 3, s4 = 4,s5 = 5,s6 = 6,s7 = 7,s8 = 8,s9 = 9,s10 = 10;
    reg [3:0] state,next_state;
    
    always @(posedge clk) begin
        if(reset)
            state <= s1;
        else 
            state <= next_state;
    end
    always @(*) begin
        case(state)
            s1: begin next_state = data ? s2 : s1; end
            s2: begin next_state = data ? s3 : s1; end
            s3: begin next_state = data ? s3 : s4; end
            s4: begin next_state = data ? s5 : s1; end
            s5: begin next_state = s6; end
            s6: begin next_state = s7; end
            s7: begin next_state = s8; end
            s8: begin next_state = s9; end
            s9: begin next_state = done_counting ? s10 : s9; end
            s10 : begin  next_state = ack ? s1 : s10; end
            default : next_state = s1;
        endcase
    end
    
    assign shift_ena = (state == s5 || state == s6 || state == s7 || state == s8);
    assign counting = state == s9;
    assign done = state == s10;
endmodule

6 The complete timer

7 FSM: One-hot logic equations