UVM Systemverilog SystemC EDA IP国外学习网站

UVM Systemverilog SystemC EDA IP国外学习网站【转载】

EDA | IP | TOOL:

  1. Avery Design Systems (avery-design.com)

  2. https://www.syosil.com/

  3. IEEE

  4. Build Reliable Products | Amiq

  5. Design And Reuse, The System-On-Chip Design Resource - IP, Core, SoC (design-reuse.com)

  6. Agnisys | Best Products & Services for System Verilog / UVM

  7. Arteris IP = The leaders in SoC System IP

  8. Jira | Issue & Project Tracking Software | Atlassian

  9. Magillem: EDA Front-end design and documentation software

  10. Home – OneSpin Solutions

  11. www.verilab.com

  12. Semiconductor Engineering - Deep Insights For Chip Engineers (semiengineering.com)

  13. LCDM-ENG

  14. The Design Verification Company - Aldec, Inc

  15. opentitan

  16. Hardware Design Verification & Validation | ProGineer Technologies

  17. Welcome to SmartDV Technologies (smart-dv.com)

  18. Home - FirstEDA

  19. Rugged High-Performance Interfaces and Computing Solutions | New Wave DV

  20. Edaphic.Studio

  21. Correct Designs

  22. BestTech Views

  23. TrueChip

  24. Symbiotic EDA Empowerment

  25. https://edacafe.com

  26. DesignCon

  27. The open source digital design conference
  28. Design Automation Conference (dac.com)

  29. Formal Methods in Computer-Aided Design
  30. Breker--Advanced Verification Solutions


  31. Home | axiomise

  32. SynaptiCAD

SystemC专区:

TODO

Here are few good resources to refer & learn about UVM:
  1. Verification Academy

    www.verificationacademy.com

  2. Accellera System Initiative

    www.accellera.org

  3. UVM Cookbook

    UVM | Verification Academy

  4. Coverage Cookbook

    Coverage | Verification Academy

  5. UVM Coding Guidelines

    UVM/Guidelines | Verification Academy

  6. SystemVerilog Coding Guidelines

    SV/Guidelines | Verification Academy

  7. Doulos

    Doulos

  8. Various Papers From Cliff Cummings

    Cliff Cummings' Award-Winning Verilog & SystemVerilog Papers - many are included in Sunburst Design's Verilog Training & SystemVerilog Training Courses.

  9. Various Papers From Sutherland

    Conference Papers Authored or Co-Authored by Stuart Sutherland

  10. testbench.in

    www.testbench.in

  11. asic-world.com

    www.asic-world.com

  12. AMBA (AXI, AHB) Protocols

    AMBA Specifications for On-Chip Connectivity – Arm®

  13. Synopsys SNUG Papers

    http://www.synopsys.com/community/snug/pages/proceedings.aspx

  14. Cadence CDNLive Papers

    Cadence Events

  15. Mentor’s Verification Horizons

    Verification Horizons | Siemens Digital Industry Software   Questa Advanced Verification Environment for Simulation and Debug | Siemens Digital Industries Software

You may like to use following online Simulator & data storage cum configuration management site:

www.edaplayground.com

www.github.com

I will look forward to add more resources in future which might be beneficial for you!

Good Day!

本文转自 https://blog.csdn.net/Holden_Liu/article/details/102685690,如有侵权,请联系删除。

Table of Contents Articles Introduction 0 Cookbook/Introduction 0 Cookbook/Acknowledgements 1 Testbench Architecture 2 Testbench 2 Testbench/Build 9 Testbench/Blocklevel 19 Testbench/IntegrationLevel 29 Component 39 Agent 42 Phasing 48 Factory 53 UsingFactoryOverrides 56 SystemVerilogPackages 62 Connections to DUT Interfaces 65 Connections 65 SVCreationOrder 71 Connect/SystemVerilogTechniques 73 ParameterizedTests 75 Connect/Virtual Interface 78 Config/VirtInterfaceConfigDb 86 Connect/VirtInterfacePackage 90 Connect/VirtInterfaceConfigPkg 93 Connect/TwoKingdomsFactory 97 DualTop 103 VirtInterfaceFunctionCallChain 106 BusFunctionalModels 108 ProtocolModules 111 Connect/AbstractConcrete 115 Connect/AbstractConcreteConfigDB 118 Configuring a Test Environment 126 Configuration 126 Resources/config db 131 Config/Params Package 134 Config/ConfiguringSequences 139 ResourceAccessForSequences 142 MacroCostBenefit 145 Analysis Components & Techniques 146 Analysis 146 AnalysisPort 149 AnalysisConnections 152 MonitorComponent 158 Predictors 161 Scoreboards 163 MetricAnalyzers 170 PostRunPhases 172 Matlab/Integration 175 End Of Test Mechanisms 183 EndOfTest 183 Objections 185 Sequences 188 Sequences 188 Sequences/Items 193 Transaction/Methods 195 Sequences/API 200 Connect/Sequencer 204 Driver/Sequence API 206 Sequences/Generation 213 Sequences/Overrides 221 Sequences/Virtual 223 Sequences/VirtualSequencer 231 Sequences/Hierarchy 237 Sequences/SequenceLibrary 242 Driver/Use Models 246 Driver/Unidirectional 247 Driver/Bidirectional 250 Driver/Pipelined 255 Sequences/Arbitration 267 Sequences/Priority 276 Sequences/LockGrab 277 Sequences/Slave 284 Stimulus/Signal Wait 290 Stimulus/Interrupts 294 Sequences/Stopping 301 Sequences/Layering 302 Register Abstraction Layer 308 Registers 308 Registers/Specification 315 Registers/Adapter 317 Registers/Integrating 321 Registers/Integration 327 Registers/RegisterModelOverview 332 Registers/ModelStructure 334 Registers/QuirkyRegisters 344 Registers/ModelCoverage 349 Registers/BackdoorAccess 354 Registers/Generation 357 Registers/StimulusAbstraction 358 Registers/MemoryStimulus 370 Registers/SequenceExamples 375 Registers/BuiltInSequences 382 Registers/Configuration 386 Registers/Scoreboarding 389 Registers/FunctionalCoverage 395 Testbench Acceleration through Co-Emulation 401 Emulation 401 Emulation/SeparateTopLevels 404 Emulation/SplitTransactors 410 Emulation/BackPointers 415 Emulation/DefiningAPI 419 Emulation/Example 422 Emulation/Example/APBDriver 430 Emulation/Example/SPIAgent 435 Emulation/Example/TopLevel 441 Debug of SV and UVM 444 BuiltInDebug 444 Reporting/Verbosity 455 UVM/CommandLineProcessor 460 UVM Connect - SV-SystemC interoperability 464 UvmConnect 464 UvmConnect/Connections 466 UvmConnect/Conversion 468 UvmConnect/CommandAPI 472 UVM Express - step by step improvement 476 UvmExpress 476 UvmExpress/DUT 481 UvmExpress/BFM 485 UvmExpress/WritingBfmTests 490 UvmExpress/FunctionalCoverage 498 UvmExpress/ConstrainedRandom 503 Appendix - Deployment 516 OVM2UVM 516 OVM2UVM/DeprecatedCode 527 OVM2UVM/SequenceLibrary 528 OVM2UVM/Phasing 530 OVM2UVM/ConvertPhaseMethods 535 UVC/UvmVerificationComponent 537 Package/Organization 548 Appendix - Coding Guidelines 555 SV/Guidelines 555 UVM/Guidelines 569 Appendix - Glossary of Terms 579 Doc/Glossary 579
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