目录 1. Introduction Link and Lanes Differential 1.1. Signaling rate Bandwidth 2. PCIe Frabric Topology 2.1. Transport Model 2.2. Memory Mapped 3. Layering 4. 4KB Configuration Register Space 5. Riffa 6. Xilinx PCIe IP 6.1. 7 Series Integrated Block for PCI Express 6.2. AXI Memory Mapped To PCI Express IP 6.3. DMA/Bridge Subsystem for PCI Express (PCIe)(XDMA) PCIe 学习资源 PCIe总线-PCIe总线简介(一) pcie 详解