module rom(clk,addm,cs_n,dout);
input clk,cs_n;
input [2:0] addm;
output [7:0] dout;
reg [7:0] dout;
reg [7:0] rom [7:0];
initial begin
rom[0] = 8'b0000_0000;
rom[1] = 8'b0000_0001;
rom[2] = 8'b0000_0010;
rom[3] = 8'b0000_0011;
rom[4] = 8'b0000_0100;
rom[5] = 8'b0000_0101;
rom[6] = 8'b0000_0110;
rom[7] = 8'b0000_0111;
end
always @ (posedge clk) begin
if(cs_n)
dout <= 8'bzzzz_zzzz;
else
dout <= rom[addm];
end
endmodule
`timescale 1ns/1ns
module rom_tb;
reg clk,cs_n;
reg [2:0] addm;
wire [7:0] dout;
rom n1 (clk,addm,cs_n,dout);
initial begin
clk = 0; addm = 0; cs_n= 0;
end
always begin
#10 clk = ~clk;
end
initial begin
repeat(7)
#20 addm = addm+1;
end
//#200 $finish;
endmodule
深度为8,位宽为8 bit的ROM
最新推荐文章于 2024-03-07 22:25:43 发布