SVA学习小结

SVA学习小结
1、基本概念
1)为什么要使用断言(assertions)?
断言主要用于检查设计的行为是否正常。可以用来提供功能覆盖信息,断言可以分为立即断言和并发断言。
2)什么是立即断言(Immediate assertions)和并发断言(concurrent assertion)?
立即断言:当使用if或assert()执行语句时,立即断言检查表达式是否为真。
并发断言:并发断言通过使用property持续检查仿真过程中的信号值。
2、语法层次结构
1)基础语法结构:主要包括五部分
(1)最底层时布尔表达式
(2)第二层时序列(sequence),其中包含一些新的操作符,如##时隙延迟,重复操作符,序列操作符等,序列是一个分装格式,采用序列封装后可以在不同的地方使用,一个序列会被评估为真或者假,
(3)第三层是属性(property),这是重要的封装方式,其中最重要的特点是属性内部可以定义蕴涵操作符(| - >、|=>)
(4)第四层是断言指示层,也就是采用assert对特定属性或者序列做行为检查,或者采用cover做统计等
(5)第五层是断言的封装,只有通过最后的封装成一个单元的断言模块才可以在不同的地方重用,就如同一个可以例化模块或类,通常这一层会通过module,program,interface来封装
2)bind
为了实现验证和设计分离,SV支持通过bind(绑定)将断言属性封装模块绑定到任意的设计模块或者其特定例化中,这个功能可以实现以下几个目的:
(1)验证工程师可以最少的改动原有的设计代码或文件结构
(2)验证IP可以方便绑定到特定的设计模块或者例化中
(3)对现有的断言没有任何语法上的影响,断言可以通过这种方式实现层次化的访问

There are some simple tricks that every design engineer should know to facilitate the usage of SystemVerilog Assertions. Although this paper is not intended to be a comprehensive tutorial on SystemVerilog Assertions, it is worthwhile to give a simplified definition of a property and the concurrent assertion of a property. 1.1 What is an assertion? An assertion is basically a "statement of fact" or "claim of truth" made about a design by a design or verification engineer. An engineer will assert or "claim" that certain conditions are always true or never true about a design. If that claim can ever be proven false, then the assertion fails (the "claim" was false). Assertions essentially become active design comments, and one important methodology treats them exactly like active design comments. More on this in Section 2. A trusted colleague and formal analysis expert[1] reports that for formal analysis, describing what should never happen using "not sequence" assertions is even more important than using assertions to describe always true conditions. 1.2 What is a property? A property is basically a rule that will be asserted (enabled) to passively test a design. The property can be a simple Boolean test regarding conditions that should always hold true about the design, or it can be a sampled sequence of signals that should follow a legal and prescribed protocol. For formal analysis, a property describes the environment of the block under verification, i.e. what is legal behavior of the inputs. 1.3 Two types of SystemVerilog assertions SystemVerilog has two types of assertions: (1) Immediate assertions (2) Concurrent assertions Immediate assertions execute once and are placed inline with the code. Immediate assertions are not exceptionally useful except in a few places, which are detailed in Section 3.
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