vmm_opts::get_int

Some of the test parameters in functional verification are passed from the command line. Passing Parameters from the command line allows simulating the same testcase file with different scenario. Fo
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vmm_opts是vmm的系统类,包含了3个函数,get_int(),get_string(),get_bit();

利用opts函数,可以大大提高代码的重复利用率。

simv +vmm_opts+FOO=HELLO

simv +vmm_opts+FOO=100


参考文献 : http://www.testbench.in/VM_12_VMM_OPTS.html

Some of the test parameters in functional verification are passed from the command line. Passing Parameters from the command line allows simulating the same testcase file with different scenario. For example, let say you are verifying Ethernet protocol. Insert_crc_error.sv is a testcase file which verifies the DUT by sending CRC error packets. Now you can use the same testcase file to verify the DUT in 3 different modes , 10G 1000M and 100M modes by passing these parameters from the command prompt, this increases the testcase reusability. 


As parameters became one of the most important techniques in reusing the testcases, vmm has added vmm_opts class to manage parameters efficiently.  
vmm_opts captures parameter from run time options. 

There are 2 ways to specify the parameters during runtime.  

 1) Command line 
vmm_opts internally uses $plusargs to recognize the options specified on command line. 
 2) text file  
If you have lot of parameters to mentions, then you can also mention all the parameters in a text file and pass it as command line options. 

vmm_opts can recognize 3 types of parameters. They are  

 String type parameters  
 Integer type parameters  
 Bit type parameters  

Following are the 3 static methods which are defined in vmm_opts to get the parameter values.  


Static  function   bit  get_bit ( string   name ,   string  doc  =   "" );  

Static  function   int  get_int ( string
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class vbase_test extends uvm_test; `uvm_component_utils(vbase_test) env m_env; vseqr m_vseqr; int unsigned simSeed; function new(string name, uvm_component parent); super.new(name, parent); endfunction : new extern function void build_phase (uvm_phase phase); extern function void connect_phase (uvm_phase phase); extern task reset_phase(uvm_phase phase); extern task reset_reg_model(); extern function void end_of_elaboration_phase(uvm_phase phase); extern function void start_of_simulation_phase(uvm_phase phase); extern task main_phase(uvm_phase phase); // report test result extern virtual function void report_phase(uvm_phase phase); endclass : vbase_test function void vbase_test::build_phase (uvm_phase phase); super.build_phase(phase); m_env = env::type_id::create(.name("m_env"), .parent(this)); // virtual sequencer m_vseqr = vseqr::type_id::create(.name("m_vseqr"), .parent(this)); uvm_config_db# (uvm_object_wrapper)::set(this,"m_vseqr.main_phase","default_sequence",vBaseSeq::type_id::get()); //uvm_config_db# (uvm_object_wrapper)::set(this,"m_vseqr.main_phase","default_sequence",vUniBaseSeq#()::type_id::get()); endfunction : build_phase function void vbase_test::connect_phase (uvm_phase phase); m_vseqr.p_rm = m_env.m_reg_model; m_vseqr.i2c_seqr = m_env.m_i2c_agent.m_seqr; endfunction : connect_phase task vbase_test::reset_phase(uvm_phase phase); //`uvm_info(get_type_name(), {"REGISTER MODEL:\n", m_reg_model.sprint()}, UVM_MEDIUM) reset_reg_model(); super.reset_phase(phase); endtask task vbase_test::reset_reg_model(); forever begin wait (tb_top.reset_n == 0); m_env.m_reg_model.reset(); `uvm_info(get_type_name(), "Reseting Complete", UVM_MEDIUM) wait (tb_top.reset_n == 1); end endtask function void vbase_test::end_of_elaboration_phase(uvm_phase phase); int handle; $system("rm -rf TEST_RUNNING"); simSeed = $get_initial_random_seed(); handle = $fopen($psprintf("TEST_RUNNING_%0d",simSeed),"w"); $fclose(handle); handle = $fopen("caseSeed","w"); $fwrite(handle,"%0d",simSeed); $fclose(handle); if($test$plusargs("uvm_tree")) uvm_top.print_topology(); endfunction : end_of_elaboration_phase function void vbase_test::start_of_simulation_phase(uvm_phase phase); `uvm_info(get_type_name(), {"start of simulation for ", get_full_name()}, UVM_HIGH); endfunction : start_of_simulation_phase task vbase_test::main_phase(uvm_phase phase); phase.phase_done.set_drain_time(this, 200ns); endtask : main_phase // report test result function void vbase_test::report_phase(uvm_phase phase); uvm_report_server server; int handle; int unsigned err_num; super.report_phase(phase); server = get_report_server(); err_num = (server.get_severity_count(UVM_ERROR) + server.get_severity_count(UVM_FATAL)); simSeed = $get_initial_random_seed(); $display("\n********************************************************************************************\n"); if (err_num != 0) begin $display("TEST CASE FAILED!!!"); handle = $fopen($psprintf("TEST_FAILED_%0d",simSeed),"w"); end else begin $display("TEST CASE PASSED!!!"); handle = $fopen($psprintf("TEST_PASSED_%0d",simSeed),"w"); end $fclose(handle); $display("\n********************************************************************************************\n"); $system("rm -rf TEST_RUNNING*"); endfunction `endif
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