可调时时钟 verilog模块
1、该设计的主要点在于调整信号的产生,即按键的处理。在100khz的时钟下,产生按键前后的变化信号,此方法可代替检测按键边沿信号并消抖的模式。
//-------------------------生成调整信号-----------------------------
wire hour_adj ;
wire sec_adj ;
wire min_adj ;
reg hour_d1 = 0;
reg hour_d2 = 0;
reg min_d1 = 0;
reg min_d2 = 0;
reg sec_d1 = 0;
reg sec_d2 = 0;
always @ ( posedge clock_100k )
begin
hour_d1 <= key[2];
hour_d2 <= hour_d1;
min_d1 <= key[1];
min_d2 <= min_d1;
sec_d1 <= key[0];
sec_d2 <= sec_d1;
end
assign hour_adj = key[3]&&( hour_d1 & (~hour_d2) );
assign min_adj = key[3]&&(min_d1 & (~min_d2));
assign sec_adj = key[3]&&(sec_d1 & (~sec_d2));
2、时钟计数器设计,生成时分秒信号,若按键信号有效,则按照相应按键处理。
//---------------------sec计数器处理----------------------
always @ ( posedge clock_100k ,negedge reset)
begin
if (! reset )
cnt_sec_r <= 0;
else if ( cnt_sec_r <=9 )
begin
if ( sec_adj )
cnt_sec_r <= cnt_sec_r + 1;
else if ( cnt == 99999 )//99999
cnt_sec_r <= cnt_sec_r + 1;
end
else
cnt_sec_r <= 0;
end
always @ ( posedge clock_100k ,negedge reset)
begin
if ( !reset)
cnt_sec_rr <= 0;
else if ( cnt_sec_rr <= 5 )
begin
if ( sec_adj && cnt_sec_r ==9)
cnt_sec_rr <= cnt_sec_rr + 1;