HDLBits练习——Mt2015 muxdff

Taken from ECE253 2015 midterm question 5

Consider the sequential circuit below:

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

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前言

四个输入，包括一个时钟clk，一个二路选择器的选择信号，一个二路选择器1端的输入信号r_in，一个二路选择器0端的输入信号q_in；一个输出信号Q。

代码

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    always@(posedge clk)begin
        Q<=L?r_in:q_in;
    end
endmodule

总结

对于如图所示重复且有规律的电路，例化模块是最佳的选择。