Verilog练习：HDLBits笔记11

四、Sequential Logic  

Latches and Flip-Flops

1、D flip-flop

Problem Statement：

Create a single D flip-flop.

module top_module (
    input clk,    
    input d,
    output reg q 
);
    always@(posedge clk)begin
    	q = d;
    end

endmodule

 2、D flip-flops

Problem Statement：

Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)begin
        q[7:0] = d[7:0];
    end

endmodule

  3、DFF with reset

Problem Statement：

Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input reset,           
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)begin
        if(reset == 1'b1)
            q[7:0] = 8'd0;
        else 
            q[7:0] = d[7:0];
    end

endmodule

  4、DFF with reset value

Problem Statement：

Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk)begin
        if(reset == 1'b1)
            q[7:0] = 8'h34;
        else 
            q[7:0] = d[7:0];
    end

endmodule

 4、DFF with asynchronous reset

Problem Statement：

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input areset,   
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset)begin
        if(areset == 1'b1)
            q = 8'd0;
        else 
            q = d;
    end

endmodule

 5、DFF with byte enable

Problem Statement：

Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].

resetn is a synchronous, active-low reset.

All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk)begin
        if(!resetn)
            q <= 16'd0;
        else if(byteena[0] || byteena[1] == 1'b1)begin
        	if(byteena[0] == 1'b1)
            	q[7:0] <= d[7:0];
       		if(byteena[1] == 1'b1)
            	q[15:8] <= d[15:8];
        end
    end
    
endmodule

 6、D Latch

Problem Statement：

Implement the following circuit:

module top_module (
    input d, 
    input ena,
    output q
);
    always@(*)begin
        if(ena == 1'b1)
    		q <= d;
    end

endmodule

 7、DFF

Problem Statement：

Implement the following circuit:

module top_module (
    input clk,
    input d, 
    input ar,   
    output q
);
    always@(posedge clk or posedge ar)begin
        if(ar)
            q <= 0;
        else 
            q <= d;
    end

endmodule

  8、DFF

 Problem Statement：

Implement the following circuit:

module top_module (
    input clk,
    input d, 
    input r,  
    output q
);
    always@(posedge clk)begin
        if(r)
            q <= 0;
        else 
            q <= d;
    end

endmodule

  9、DFF + gate

Problem Statement：

Implement the following circuit:

module top_module (
    input clk,
    input in, 
    output out
);
    wire out1;
    
    assign out1 = out ^ in;
    
    always@(posedge clk)begin
    	out <= out1;
    end

endmodule

  10、MUX and DFF

Problem Statement：

Consider the sequential circuit below:

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q
);
    
    always @(posedge clk) begin
        Q <= L ? r_in : q_in;
    end

endmodule

 11、MUX and DFF

Problem Statement：

Consider the n-bit shift register circuit shown below:

Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    always@(posedge clk)begin
        Q <= L ? R : (E ? w : Q) ;
    end

endmodule

  12、DFFs and Gates

Problem Statement：

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

module top_module (
    input clk,
    input x,
    output z
); 
    reg[2:0]q;
    
    always@(posedge clk)begin
        q[0] <= x ^ q[0];
        q[1] <= x & ~q[1];
        q[2] <= x | ~q[2];
    end
    
    assign z = ~(q[2] | q[1] | q[0]);

endmodule

 13、Create circuit from truth table 

Problem Statement：

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

J	K	Q
0	0	Qold
0	1	0
1	0	1
1	1	~Qold

module top_module (
    input clk,
    input j,
    input k,
    output Q
); 
    always@(posedge clk)begin
        case({j,k})
        	2'b00 : Q <= Q;
            2'b01 : Q <= 0;
            2'b10 : Q <= 1;
            2'b11 : Q <= ~Q;
        endcase
    end

endmodule

  14、Detect an edge

Problem Statement：

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]in_d0;
    reg [7:0]in_d1;
    
    always@(posedge clk)begin
        in_d0 <= in;
        in_d1 <= in_d0;
    end
    
    assign pedge = ~in_d1 & in_d0;
        
endmodule

  15、Detect both edges

Problem Statement：

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);

    reg [7:0]in_d0;
    reg [7:0]in_d1;
    
    always@(posedge clk)begin
        in_d0 <= in;
        in_d1 <= in_d0;
    end
    
    assign anyedge = (~in_d1 & in_d0) | (in_d1 & ~in_d0);
        
endmodule

16、Edge capture register

Problem Statement：

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity. 

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0]in_d0;
    
    always@(posedge clk)begin
        in_d0 <= in;
        if(reset == 1'b1)
            out <= 32'd0;
        else 
            out  = (~in & in_d0) | out; 
    end
     

endmodule

17、Dual-edge capture register 

Problem Statement：

 A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:

module top_module (
    input clk,
    input d,
    output q
);
    reg p,n;
    
    always@(posedge clk)begin
        p <= d ^ n;		
    end
    always@(negedge clk)begin
        n <= d ^ p;		
    end    
    assign q = p ^ n;

endmodule