【verilog学习17】HDLBits：Circuits_Sequential Logic_Latches and Flip-Flops

I. D flip-flop (Dff)

1.代码编写

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
	always@(posedge clk)
		q <= d;
endmodule

2.提交结果

success

3.题目分析

A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.

D flip-flops are created by the logic synthesizer when a clocked always block is used (See alwaysblock2). A D flip-flop is the simplest form of “blob of combinational logic followed by a flip-flop” where the combinational logic portion is just a wire.

Create a single D flip-flop.

D触发器是一种在（通常）时钟信号的正边缘存储位并定期更新的电路。
D触发器由逻辑合成器在使用时钟始终块时创建。D触发器是“组合逻辑的blob后跟一个触发器”的最简单形式，其中组合逻辑部分只是一根导线。
创建一个D触发器。

II. D flip-flops (Dff8)

1.代码编写

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk) begin
            q <= d;
    end
endmodule

2.提交结果

success

3.题目分析

Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.
8个D-触发器并行。

III. Dff with reset (Dff8r)

1.代码编写

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)
        q <= (reset)? 8'd0:d;
endmodule

2.提交结果

success

3.题目分析

Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.
带同步置零的8-bit寄存器。

IV. Dff with reset value (Dff8p)

1.代码编写

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk)
        q <= (reset)? 8'h34:d;
endmodule

2.提交结果

success

3.题目分析

Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.
Hint:Resetting a register to ‘1’ is sometimes called “preset”（将寄存器重置为“1”有时称为“预设”）。
创建一个时钟下降沿触发、同步置位至0x34(8’h34)的8-bit寄存器。

V. DFF with asynchronous reset (Dff8ar)

1.代码编写

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk,posedge areset)
        q <= (areset)? 8'd0:d;
endmodule

2.提交结果

success

3.题目分析

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.
异步置位（与同步置位仅仅是敏感列表的差别）。

• 同步置位：触发器在时钟信号的激励下，在时钟信号的上升/下降沿被置位。
• 异步置位：触发器在置位信号的激励下，在置位信号的上升/下降沿被置位。
  同时，他也是一个高电平置位，所以需判断 areset=1 的条件下被置位。

VI. DFF with byte enable (Dff16e)

1.代码编写

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk) begin
        if(~resetn) q <= 16'd0;
        else begin
            case(byteena)
                2'b00: q <= q;
                2'b01: q <= {q[15:8],d[7:0]};
                2'b11: q <= d;
                2'b10: q <= {d[15:8],q[7:0]};
            endcase
        end
    end
endmodule

2.提交结果

success

3.题目分析

Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, active-low reset.
All DFFs should be triggered by the positive edge of clk.

同步、低电平置位，时钟上升沿触发，byteena[1]控制d[15:8]可写入q[15:8]，byteena[0]控制d[7:0]可写入q[7:0]。

VII. D Latch (Exams/m2014 q4a)

1.代码编写

module top_module (
    input d, 
    input ena,
    output q);
    always@(*) begin
        if(ena)
            q <= d;
    end
endmodule

2.提交结果

success

3.题目分析

Hint：

• Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
• However, they are still sequential elements, so should use non-blocking assignments.
• A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.
  采用“无敏感列表”，当ena=1使能，用非阻塞赋值 q<=d，否则，系统维持原输出，形成锁存器。
  尽管用了无敏感列表always@(*)，但锁存器依然是一个时序逻辑元件，应该用非阻塞赋值。

VIII. DFF (Exams/m2014 q4b)

1.代码编写

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always@(posedge clk,posedge ar) begin
        q <= (ar)? 1'b0:d;
    end
endmodule

2.提交结果

success

3.题目分析

一个带有异步置位，高电平置位的D触发器。

IX. DFF (Exams/m2014 q4c)

1.代码编写

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always@(posedge clk)
        q <= (r)? 1'b0:d;
endmodule

2.提交结果

success

3.题目分析

与第八题同理，这是一个 同步置位、高电平置位的D触发器。

VII. DFF+gate (Exams/m2014 q4d)

1.代码编写

module top_module (
    input clk,
    input in, 
    output out);
    always@(posedge clk) begin
        out <= in^out;
    end
endmodule

2.提交结果

success

3.题目分析

需要实现这样一个电路：D触发器的输出out与输入in相异或，共同作为下一个时钟上升沿到来时D触发器的输入。

X. Mt2015 muxdff (Mux and DFF)

1.代码编写

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    always@(posedge clk)
        Q <= (L)? r_in:q_in;
endmodule

2.提交结果

success

3.题目分析

Taken from ECE253 2015 midterm question 5
Consider the sequential circuit below:

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.
需要为这个电路设计它的submodule，由于这是一个2to1MUX，所以没有用case语句。

XI. Mux and DFF (Exams/2014 q4a)

1.代码编写

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
	wire in2;
    assign in2 = (E)? w:Q;
    always@(posedge clk)
        Q <= (L)? R:in2;
endmodule

2.提交结果

success

3.题目分析

Consider the n-bit shift register circuit shown below:

Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.
实现电路的一级，仍是相当于写一个submodule。

XII. DFFs and gates (Exams/ece241 2014 q4)

1.代码编写

module top_module (
    input clk,
    input x,
    output z
); 
    wire Q1,Q2,Q3;
    wire iQ2,iQ3;
    D_ff instance1(.clk(clk),.D(x^Q1),.Q(Q1),.iQ());
    D_ff instance2(.clk(clk),.D(x&iQ2),.Q(Q2),.iQ(iQ2));
    D_ff instance3(.clk(clk),.D(x|iQ3),.Q(Q3),.iQ(iQ3));
    assign z = ~(Q1|Q2|Q3);
endmodule
module D_ff(
	input clk,
	input D,
	output Q,
    output iQ);
    assign iQ=~Q;
    always@(posedge clk) begin
        Q <= D;
    end
endmodule 

2.提交结果

success

3.题目分析

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

实现上图这样一个电路。
由于硬件语言是并行的，assign相当于always@(*)连续赋值，所以在module D_ff（D Flip-flop）只需写一次assign即可完成 “保证iQ始终是Q取反，包括在第一个时钟上升沿之前” 的要求。

XIII. Create Circuit from truth table (Exams/ece241 2013 q7)

1.代码编写

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    always@(posedge clk) begin
        case({j,k})
            2'b00: Q <= Q;
            2'b01: Q <= 1'b0;
            2'b11: Q <= ~Q;
            2'b10: Q <= 1'b1;                
        endcase 
    end
endmodule

2.提交结果

Success

3.题目分析

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

有两个（多个）条件时，在case语句中可以先拼接起来，再写分支表达式。

XIV. Detect an edge (Edgedetect)

1.代码编写

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    wire [7:0] in_ini;
    always@(posedge clk) begin
        in_ini <= in;
        pedge <= ~in_ini&in;
    end
endmodule

2.提交结果

Success

3.题目分析

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

需要知道in的“上一状态”，由于时延的存在，即非阻塞赋值的作用

        in_ini <= in;
        pedge <= ~in_ini&in;

在时钟上升沿为 <= 赋值，第一个语句的in是这个时钟周期的in，第二个语句的in_ini还是上个时钟周期的in，在时钟周期结束时一同赋给 <= 左侧。

· 非阻塞赋值是由时钟节拍决定，在时钟上升到来时，执行 赋值 语句右边，然后将begin-end之间的所有赋值语句同时赋值到赋值语句的左边，注意：是begin—end之间的所有语句，一起执行，且一个时钟只执行一次。
· (尽管 begin_end 是一个串行块)

XV. Detect both edges (Edgedetect2)

1.代码编写

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    wire [7:0] in_ini;
    always@(posedge clk) begin
        // 只要in变了就置anyedge 0->1
        in_ini <= in;
        anyedge <= in_ini^in;
    end
endmodule

2.提交结果

Success

3.题目分析

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

XVI. Edge Capture register (Edgecapture)

1.代码编写

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    wire [31:0] in_ini;
    always@(posedge clk) begin
        in_ini <= in;
        out <=(reset)? 32'd0:in_ini&~in | out;
    end
endmodule

2.提交结果

Success

3.题目分析

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

进行下降沿检测，out为1的bit位保持为1，直至收到同步置位的reset为高（Capture）。

XVII. Dual-edge triggered flip-flop (Dualedge)

1.代码编写

module top_module (
    input clk,
    input d,
    output q
);
    wire q2,q3;
    p_Dff(.clk(clk),.d(d),.q(q2));
    n_Dff(.clk(clk),.d(d),.q(q3));
    assign q = (clk)? q2:q3;
endmodule
module p_Dff(
	input clk,
	input d,
    output q);
    always@(posedge clk)
        q <= d;
endmodule
module n_Dff(
	input clk,
	input d,
    output q);
    always@(negedge clk)
        q <= d;
endmodule

2.提交结果

Success

3.题目分析

You’re familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don’t have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:

(Note: It’s not necessarily perfectly equivalent: The output of flip-flops have no glitches, but a larger combinational circuit that emulates this behaviour might. But we’ll ignore this detail here.)
Hint…

• You can’t create a dual-edge triggered flip-flop on an FPGA. But you can create both positive-edge triggered and negative-edge triggered flip-flops.
• This problem is a moderately difficult circuit design problem, but requires only basic Verilog language features. (This is a circuit design problem, not a coding problem.) It may help to first sketch a circuit by hand before attempting to code it.

FPGA中不含有双边触发器，所以可以设计一个上升沿触发器和一个下降沿触发器，再根据clk的状态，若clk=0 / 1，代表刚刚经历的是下降沿 / 上升沿，选择从下降沿 / 上升沿触发器输出。
这是一道中等难度的题，但这其实是一道电路题而非一道代码题，想一想电路构成即可。