Exams/ece241 2014 q7a

最新推荐文章于 2024-05-06 23:37:37 发布

eachanm

最新推荐文章于 2024-05-06 23:37:37 发布

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分类专栏： HDLBits题目文章标签： fpga开发

本文链接：https://blog.csdn.net/eachanm/article/details/131077754

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该文描述了一个4位同步计数器的设计，包括重置、使能和时钟输入，以及计数器的输出。在重置信号为高或计数值达到12时，加载信号和数据输入被设置以重新开始计数。使用了一个已提供的4位计数器模块count4，并通过c_enable,c_load和c_d信号控制内部计数器的操作。

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Design a 1-12 counter with the following inputs and outputs:

Reset Synchronous active-high reset that forces the counter to 1
Enable Set high for the counter to run
Clk Positive edge-triggered clock input
Q[3:0] The output of the counter
c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.

You have the following components available:

the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
logic gates

module count4(
	input clk,
	input enable,
	input load,
	input [3:0] d,
	output reg [3:0] Q
);

The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

没咋看懂这题目，看代码就好理解了

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
    
    assign  c_enable = enable;
    always@ (*)
        if(reset) begin
        	c_load <= 1'b1;
            c_d <= 4'd1;
        end
        else if(enable == 1'b1 && Q == 4'd12) begin
             c_load <= 1'b1;
             c_d <= 4'd1;
        end
    	else begin
            c_load <= 1'b0;
            c_d <= 4'd0;
        end
                
     
    
    
    count4 the_counter (
        .clk(clk), 
        .enable(c_enable), 
        .load(c_load), 
        .d(c_d),
        .Q(Q)
    );

endmodule