7nm项目——floorplan

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已于 2023-10-20 11:56:14 修改

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分类专栏： 7nm Cortex-A53 项目学习经验合集文章标签：学习

于 2023-08-10 23:16:14 首次发布

本文链接：https://blog.csdn.net/tong66666666/article/details/132219369

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### read floorplan def if specified

-------------------------------------------------------------------
# create row: created during initialize_floorplan, only necessary when customized rows are needed
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_create_site_rows.tcl

#-------------------------------------------------------------------
# create tracks
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_create_tracks.tcl

value值是以后摆放st cell 依据

M0宽度不均

cell出pin依赖于M1 track小箭头

#-------------------------------------------------------------------
# insert manufature cells
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_insert_manufacture_cell.tcl

#-------------------------------------------------------------------
### place hard macros
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_place_macros.tcl

#-------------------------------------------------------------------
### legalize hard macros
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_legalize_fp_objects.tcl

pin和track对齐，颜色也对上

#-------------------------------------------------------------------
# create voltage areas
#-------------------------------------------------------------------

#-------------------------------------------------------------------
# create bounds
#-------------------------------------------------------------------

#-------------------------------------------------------------------
# create groups
#-------------------------------------------------------------------

#-------------------------------------------------------------------
# place ports
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_place_ports.tcl

#-------------------------------------------------------------------
# create keepout margin around hard macros
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_create_keepout_margin.tcl

#-------------------------------------------------------------------
# create placement blockages #-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_create_placement_blockages.tcl

#-------------------------------------------------------------------
# boundary cells
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_create_boundary_cells.tcl

#-------------------------------------------------------------------

#-------------------------------------------------------------------
# create tap cells
#-------------------------------------------------------------------
cmd usr_search_execute -search_file icc2_create_tap_cells.tcl

#cmd set_att [current_design] -name design_state -value "fplan"