The S3C2440A is developed with ARM920T core,0.13um CMOS standard cells and a memory complier.
The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
The integrated on-chip functions that are described in this document include:
Around 1.2V internal,1.8V/2.5V/3.3V memory,3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU
External memory controller (SDRAM Control and Chip Select logic)
------------------------- sclk
SCLK[1:0] SDRAM clock
SCKE SDRAM clock enable
------------------------- data and addr
DQ[0-15]
A[0-12]------------------------- bank select
与BA0与BA1 连接的线,在s3c2440中没这个概念,直接用addr线代替
------------------------- control
nGCS[7:0](General Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed.// nSCS[1:0] SDRAM chip select
nSRAS SDRAM row address strobe
nSCAS SDRAM column address strobe
nWE nWE (Write Enable) indicates that the current bus cycle is a write cycle
DQM0[3:0] Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode.
#### 以下没用到
nWBE[3:0] Write byte enable