module top_module (
input clk,
input reset,
output [9:0] q);
always @(posedge clk) begin
if(reset)
q = 10'd0;
else if (q < 999)
q = q+10'd1;
else
q = 0;
end
endmodule
hdlbits.01xz.net /Circuits/Building Larger Circuits/Counter with period 1000
最新推荐文章于 2024-09-13 16:59:02 发布