低功耗验证入门——PTPX功耗分析脚本介绍

1st step 设置功耗模式

使能功耗分析：power_enable_analysis

When  set  to  true,  enables PrimePower, so that you can perform power
       analysis. Without this variable set  to  true,  you  cannot  see  power
       related  data. By default, PrimePower is disabled; this variable is set
       to false.

       If you set this variable to true and enable PrimePower, you must obtain
       a PrimePower license. You cannot use PrimePower without a license.

多轨道分析：power_enable_multi_rail_analysis

When this variable is set to true, PrimePower starts concurrent  multi-
       rail  power  analysis  power  updates. Under concurrent multirail power
       analysis mode, power data for each rails or supply nets  is  maintained
       and processed individually and concurrently. Power reports of different
       combinations of rail and supply net  specifications  can  be  generated
       without the need to update power again.

       The  -rails option of the report_power command requires that this vari-
       able is set to true.

设置功耗分析模式：power_analysis_mode

This  variable  explicitly selects the analysis mode for power calcula-
       tion.  PrimePower provides three different  analysis  modes:  averaged,
       time_based.   Set  this variable before the first power command, other-
       wise, the default mode is assumed. For a particular analysis mode,  you
       must  provide the appropriate activity information.  The allowed values
       are as follows:
       o averaged (the default): PrimePower calculates power based on  toggle-
         rate  and  state-probability.  Only averaged power results are calcu-
         lated. In this mode, it can take the VCD file and SAIF file as activ-
         ity input files. Use the set_switching_activity and set_case_analysis
         commands to set the statistical switching  activity  on  top  of  the
         default   switching   activity.    For   more  information,  see  the
         update_power man page.

       o time_based: PrimePower calculates power based on the events from VCD.
         Averaged  power  results  are calculated, along with calculations for
         peak powers and time-based power waveforms. You must provide the  VCD
         file  in this mode.  Both gate-level VCD and RTL VCD can be specified
         for this mode.  For more information, see the update_power man  page.

         The  power_analysis_mode variable can change in one run.  However, if
         you change the setting, all the activity and power  data  is  removed
         internally.   You   must  provide  activity  information  before  the
         update_power command.

         In addition, you can use the  set_power_analysis_options  to  specify
         the options for power analysis.
设置基于时钟周期的毛刺功耗分析：power_enable_clock_cycle_based_glitch

       When  set  to  true, this variable enables PrimePower to do clock cycle
       based glitch detection in time based analysis.   This  is  allowed  for
       regular  time_based flow ( VCD/FSDB with delays) or delay shifted flow.
       On a given pin/net, if there are multiple transitions or toggles within
       a  reference clock period , these transitions are categorized as glitch
       transitions.  If there are odd number of transitions ,  then  the  last
       transition  is considered as a regular transition and the rest are con-
       sidered as glitch transitions.  The power associated with glitch  tran-
       sitions will be categotized as glitch power.

       The fastest clock period in the design is considered as reference clock
       period.

       Depending on the pulse width , a glitch transition will be  categorized
       as  inertial glitch ( IG ) or transport glitch ( TG ) and this informa-
       tion  will  be  available  in  the  detailed  and  summary  report   of
       'report_power_calculation'.

       When  this  variable  is  enabled  ,  more glitch power is likely to be
       reported compared to when the variable is disabled.

       When power_enable_clock_domain_based_glitch is also enabled, then clock
       cycle  based glitch analysis is disabled and instead clock domain based
       glitch analysis is done.

设置基于时钟域的毛刺功耗分析：power_enable_clock_cycle_based_glitch

       When set to true, this variable enables PrimePower to do  clock  domain
       based  glitch  detection  in  time based analysis. Instead of using the
       fastest clock period in the design, power_base_clock of each pin/net is
       used for glitch analysis and categorization. This allows glitch catego-
       rization accuracy to improve.

       This is allowed for  both  regular  time_based  flow  (  VCD/FSDB  with
       delays)  and delay shifted flow.  On a given pin/net, if there are mul-
       tiple transitions or toggles within a  reference  clock  period,  these
       transitions  are  categorized  as glitch transitions.  If there are odd
       number of transitions , then the last transition  is  considered  as  a
       regular  transition  and the rest are considered as glitch transitions.
       The power associated with glitch transitions  will  be  categotized  as
       glitch power.

       Depending  on the pulse width , a glitch transition will be categorized
       as inertial glitch ( IG ) or transport glitch ( TG ) and this  informa-
       tion   will  be  available  in  the  detailed  and  summary  report  of
       'report_power_calculation'.

       When this variable is enabled,  more  glitch  power  is  likely  to  be
       reported compared to when the variable is disabled.

       When  power_enable_clock_cycle_based_glitch is also enabled, then clock
       cycle based glitch analysis is disabled and instead clock domain  based
       glitch analysis is done.

设置精度：report_default_significant_digits

Sets the default number of significant digits for many reports. Allowed
       values  are  0-13; the default is 2. Some report commands (for example,
       the report_timing command) have a -significant_digits option that over-
       rides the value of this variable.

       Not  all reports respond to this variable.  Check the man page of indi-
       vidual reports to determine whether they support this feature.
设置链接文件的路径：link_path

       This variable specifies a list of libraries, design files, and  library
       files used during linking. The link_design command looks at those files
       and tries to resolve references in the order that you specify.

       The link_path variable can  contain  three  types  of  elements:  *,  a
       library name, or a file name.

       The  "*"  entry  in  the  value  of  this  variable  indicates that the
       link_design command  should  search  all  the  designs  loaded  in  the
       pt_shell  while  trying  to resolve references. Designs are searched in
       the order in which they were read.

       For elements other than "*", PrimeTime searches for a library that  has
       already  been  loaded.  If  that search fails, PrimeTime searches for a
       file name using the search_path variable.

       The libraries that are specified by the link_path variable  are  loaded
       in  parallel  with  Verilog  files during the read_verilog command. For
       best runtime performance, set the search_path and  link_path  variables
       before you run the read_verilog command.
设置链接库：link_library，作用同link_path

        This is a synonym for the link_path variable.

读取网表文件：read_verilog

This command reads one or more structural, gate-level Verilog  netlists
       into  PrimeTime.   To a locate file with a relative path name, the com-
       mand  searches  for  the  file  in  each  directory  specified  by  the
       search_path  variable. The command locates a file with an absolute path
       name without considering the search_path variable.   To  determine  the
       file that the read_verilog command loads, use the which command.

       After  the  Verilog  files are loaded, view the design objects by using
       the list_designs command. To remove designs, use the remove_design com-
       mand.

       The  Verilog  netlist  must  contain  fully-mapped, structural designs.
       PrimeTime cannot link or perform timing analysis with netlists that are
       not fully mapped at the gate level. There must be no Verilog high-level
       constructs in the netlist.

读取spef或者RCdb的信息：read_parasitics

The read_parasitics command reads parasitic data from a file and  anno-
       tates  that  data  on  the nets of the current design. For best perfor-
       mance, run this command as soon as possible after the link_design  com-
       mand.

       The  command  can  read data in SPEF, DSPF, RSPF, and Galaxy Parasitics
       Database (GPD) format. For SPEF, RSPF, and DSPF, the file can be a sim-
       ple  ASCII file, or it can be compressed with gzip. The read_parasitics
       command automatically detects this format information  from  the  file,
       but you can specify the base format using the -format option.

       GPD is an efficient format for sharing parasitics among Synopsys appli-
       cations.  You can use the PrimeTime write_parasitics command to write a
       parasitics file in GPD format.

       You can specify parasitics in either reduced or detailed form.  Reduced
       parasitics consist of an RC pi model specified for each driver pin of a
       net.  An  RC pi model contains two capacitances and one resistance. The
       first capacitance connects to the net driver pin; the  resistance  con-
       nects to the net driver pin and to a subnode to which the second capac-
       itance connects. Both capacitances connect to  the  ground.  The  para-
       sitics  file, using the reduced form, also specifies the pin-to-pin net
       delays.  The RC pi model is used to compute the  effective  capacitance
       of the nets at each driver of the net. The effective capacitance deter-
       mines the cell delays and output slews. You can specify  reduced  para-
       sitics with the SPEF, DSPF, or RSPF format.

        参数：

        -keep_capacitive_coupling 添加该参数确保读入耦合电容寄生参数

        -format file_fmt 指定寄生文件类型，The allowed values  are SPEF, DSPF, RSPF, PARA (Milkyway), and GPD.

检查寄生参数反标结果：report_annotated_parasitics

        This command reports nets annotated  with  parasitics  in  the  current
       design.   This  command  can  also  check the consistency of parasitics
       after reading ascii or binary parasitics.  The  report  summarizes  how
       many nets are annotated with reduced parasitics (pi models) or detailed
       parasitics (RC networks)

链接设计文件：link_design或者link

The  link_design  locates  all  designs and library components that are
       referenced by the current design and links them to the current  design.
       During  linking,  the  tool  loads all files specified by the link_path
       variable if they are not already in memory. Successful linking  results
       in a fully instantiated design on which you can perform analysis.

       By  default,  the  case  sensitivity  of  the link is determined by the
       source of the objects being linked. Although it is not recommended, you
       can  change  the  default behavior by setting the link_force_case vari-
       able.

   Automatic Loading of Designs and Libraries
       If you set the link_path and search_path variables, you  need  to  read
       only your top-level design and then link.  The tool automatically finds
       and loads all other required designs and libraries.

       In the following example,  the  newcpu.db  top-level  design  uses  the
       cmos.db  library.   Since the link_path variable specifies cmos.db, the
       link_design command loads cmos.db. As linking proceeds, the tools loads
       any  required  design  that  is  not already in memory by searching the
       paths specified by the search_path variable. For  example,  the  refer-
       enced BOX1 design is not in memory, so the tool searches for BOX1.db in
       the search_path variable and loads it.

         pt_shell> set search_path "/designs/newcpu/v1.6/dbs /libs/cmos"
         /designs/newcpu/v1.6/dbs /libs/cmos

         pt_shell> set link_path "* cmos.db"
         * cmos.db

         pt_shell> read_db newcpu.db
         Loading db file '/designs/newcpu/v1.6/dbs/newcpu.db'
         1

         pt_shell> link_design newcpu
         Loading db file '/libs/cmos/cmos.db'
         Linking design newcpu...
         Loading db file '/designs/newcpu/v1.6/dbs/BOX1.db'
         Loading db file '/designs/newcpu/v1.6/dbs/BOX2.db'
         Loading db file '/designs/newcpu/v1.6/dbs/padring.db'
         Design 'newcpu' was successfully linked.
         1
 

检查功耗：check_power -verbose

        The  check_power  command  checks structure of the design for potential
       power violations. This command is used to identify possible power  cal-
       culation  problems  before  updating  power  or before generating power
       reports.This command also prints which checks it performs. If a check reveals a
       violation,  then the command also prints a message about the violation.
       By default, the message contains a summary of  the  violation.  To  get
       more information about violations, use the -verbose option.

计算功耗：update_power      

 Updates  power  for  the  current  design.  Power is also automatically
       updated  by  command  that  retrieves  power  results,  such   as   the
       report_power  command  and most power attributes.  Command update_power
       explicitly prepares the design for further  analysis.   Note  that  you
       must  set  variable power_enable_analysis to TRUE before any power com-
       mand.

       Starting from 2008.12 release,  update_power  can  also  perform  power
       waveform generation and peak power calculation.