verilog训练题serial receiver

In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

设置5个状态机；不同于其他的8-10个状态机。结果显示有一处没有匹配，之后自己debug发现应该没有问题。欢迎指正

//data :1014
module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output reg done
); 

parameter C_STATE_A = 3'b000;//start
parameter C_STATE_B = 3'b001; //data
parameter C_STATE_C = 3'b010; //data
parameter C_STATE_D = 3'b011; //stop
parameter C_STATE_E = 3'b100; //idle

reg [2:0] c_state = 3'b000 ;
reg [2:0] n_state = 3'b000 ;
reg [7:0] S_data_cnt;

always @(posedge clk or posedge reset) begin
    if(reset)   c_state <= 3'b000;
    else        c_state <= n_state;
end

always @(*) begin
    case(c_state)
    C_STATE_A:  begin   //start
      n_state <= C_STATE_B;
    end
    C_STATE_B:  begin
      if(S_data_cnt < 7 )
        n_state <= C_STATE_B;
      else
        n_state <= C_STATE_C;
    end
    C_STATE_C:  begin
      if(in == 1)
        n_state <= C_STATE_D;
      else
        n_state <= C_STATE_C;
    end
    C_STATE_D:  begin   //done
      if(in == 1)
        n_state <= C_STATE_E;
      else 
        n_state <= C_STATE_A;
    end
    C_STATE_E: begin    //idle
      if(in == 1)
        n_state <= C_STATE_E;
      else 
        n_state <= C_STATE_A;
    end
    endcase
end

always @(posedge clk or posedge reset) begin
    if(reset) begin
    done = 1'b0;
    S_data_cnt = 8'b0;
    end
    else begin
      case(n_state)
      C_STATE_A: begin
        done = 1'b0;
        S_data_cnt = 8'b0;
      end
      C_STATE_B: begin
        done = 1'b0;
        S_data_cnt = S_data_cnt + 1'b1;
      end
      C_STATE_C: begin
        done = 1'b0;
        S_data_cnt = S_data_cnt;
      end
      C_STATE_D: begin
        done = 1'b1;
        S_data_cnt = 8'b0;
      end
      C_STATE_E: begin
        done = 1'b0;
        S_data_cnt = 8'b0;
      end
      endcase
    end 
end
endmodule