xilinx ip 线性化与去电平

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已于 2022-11-06 17:35:54 修改

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分类专栏： xilinx ip ISP 文章标签： xilinx hls ip fpga开发 fpga

于 2022-11-06 17:19:11 首次发布

本文链接：https://blog.csdn.net/u012996559/article/details/127718002

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xilinx ip 同时被 2 个专栏收录

11 篇文章 1 订阅

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ISP

2 篇文章 7 订阅

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功能

1. 单axi-stream 接口输入（10bit raw输入），axis输出（10bit输出）。

2. 使用xilinx hls 编写。

3. 配置寄存器有

	#pragma HLS INTERFACE  s_axilite  port=blacklevelr  
	#pragma HLS INTERFACE  s_axilite  port=blacklevelb
	#pragma HLS INTERFACE  s_axilite  port=blacklevelgr
	#pragma HLS INTERFACE  s_axilite  port=blacklevelgb
	#pragma HLS INTERFACE  s_axilite  port=width
	#pragma HLS INTERFACE  s_axilite  port=height
	#pragma HLS INTERFACE  s_axilite  port=cfa

支持

支持xilinx 所有系列fpga

仿真c/rtl

对ip 进行仿真。是否能满足时序要求。

当blc 都设置为0 时候

当blc 都设置为10时候

28 对应18

ip 接口

// 0x00 : Control signals
//        bit 0  - ap_start (Read/Write/COH)
//        bit 1  - ap_done (Read/COR)
//        bit 2  - ap_idle (Read)
//        bit 3  - ap_ready (Read)
//        bit 7  - auto_restart (Read/Write)
//        others - reserved
// 0x04 : Global Interrupt Enable Register
//        bit 0  - Global Interrupt Enable (Read/Write)
//        others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
//        bit 0  - enable ap_done interrupt (Read/Write)
//        bit 1  - enable ap_ready interrupt (Read/Write)
//        others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
//        bit 0  - ap_done (COR/TOW)
//        bit 1  - ap_ready (COR/TOW)
//        others - reserved
// 0x10 : Data signal of width
//        bit 31~0 - width[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of height
//        bit 31~0 - height[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of blacklevelr
//        bit 31~0 - blacklevelr[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of blacklevelb
//        bit 31~0 - blacklevelb[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of blacklevelgr
//        bit 31~0 - blacklevelgr[31:0] (Read/Write)
// 0x34 : reserved
// 0x38 : Data signal of blacklevelgb
//        bit 31~0 - blacklevelgb[31:0] (Read/Write)
// 0x3c : reserved
// 0x40 : Data signal of cfa
//        bit 31~0 - cfa[31:0] (Read/Write)
// 0x44 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

#define XLINENAR_CONTROL_ADDR_AP_CTRL           0x00
#define XLINENAR_CONTROL_ADDR_GIE               0x04
#define XLINENAR_CONTROL_ADDR_IER               0x08
#define XLINENAR_CONTROL_ADDR_ISR               0x0c
#define XLINENAR_CONTROL_ADDR_WIDTH_DATA        0x10
#define XLINENAR_CONTROL_BITS_WIDTH_DATA        32
#define XLINENAR_CONTROL_ADDR_HEIGHT_DATA       0x18
#define XLINENAR_CONTROL_BITS_HEIGHT_DATA       32
#define XLINENAR_CONTROL_ADDR_BLACKLEVELR_DATA  0x20
#define XLINENAR_CONTROL_BITS_BLACKLEVELR_DATA  32
#define XLINENAR_CONTROL_ADDR_BLACKLEVELB_DATA  0x28
#define XLINENAR_CONTROL_BITS_BLACKLEVELB_DATA  32
#define XLINENAR_CONTROL_ADDR_BLACKLEVELGR_DATA 0x30
#define XLINENAR_CONTROL_BITS_BLACKLEVELGR_DATA 32
#define XLINENAR_CONTROL_ADDR_BLACKLEVELGB_DATA 0x38
#define XLINENAR_CONTROL_BITS_BLACKLEVELGB_DATA 32