今天把RapidIO核已经加上,相应的target user代码也已经完成,最后把VxWorks上的代码也进行了相应的调整,整个项目算是大功告成了。最后写一个简要的文档把RapidIO与Vxworks中关键的地方进行下描述以便以后查找起来理解起来也比较方便。
1. 从FLASH中加载bit文件。xxx_fpga_update_v51(g_len, g_recv_buf);
2. 判断文件大小,超过8MB为全bit;小于8MB为部分bit,并要使能部分重配置。Loacl_bus_write32(CS2_BASE, 0x38, 0x3);//可重构部分加载设置
3.重置整个系统,使得系统在一个明确的状态。hwa_dbell_send(1, 0x8000); //可重构部分使能 cpu_reset_n<= treq_db_info[0];
RapidIO--target user.v
4.开始执行FFT运算,传入待处理数据,首先判断是多少点FFT运算。Loacl_bus_read32(RAPIDIO_BASE, 0x8004, &tempVal);
5.根据第4步的判断来传入相应数据。hwa_srio_dma_send(0, (UINT32) buf, (UINT32) destptr, NUM);
localparam LAD_LOW = 24'h00_0000 >> 3;
localparam LAD_HIGH = 24'h00_7FFC >> 3;
localparam FFT_STATUS_ADDR = 24'h00_8000 >>3;
6.判断FFT运算是否完成。 Loacl_bus_read32(RAPIDIO_BASE, 0x8004, &tempVal); if ((tempVal & 0x2) == 0x2) fpga_status <= {fft_calculate_finish , 1'b1};
7.将处理完的数据传回。hwa_srio_dma_send(0, (UINT32) destptr, (UINT32) buf,NUM);
target user.v
///
//
// (c) Copyright 2005 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// rights to the materials distributed herewith. Except as
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
///
//
// File name: target_user.v
// Rev: 5.6
// Description: Target User Engine
//
///
`timescale 1 ps / 1 ps
module target_user #( parameter TCQ = 100 )(
// System Inputs
sys_clk,
lnk_reset_n,
// Target Response
tresp_prio_o,
tresp_ftype_o,
tresp_dest_id_o,
tresp_ttype_o,
tresp_status_o,
tresp_tid_o,
tresp_data_o,
tresp_sof_n_o,
tresp_eof_n_o,
tresp_vld_n_o,
tresp_dsc_n_o,
tresp_rdy_n_i,
tresp_stalls,
tresp_msg_seg,
tresp_mbox,
tresp_letter,
// Target Request
treq_prio_i,
treq_ftype_i,
treq_dest_id_i,
treq_src_id_i,
treq_tid_i,
treq_ttype_i,
treq_addr_i,
treq_byte_en_n_i,
treq_byte_count_i,
treq_data_i,
treq_sof_n_i,
treq_eof_n_i,
treq_vld_n_i,
treq_rdy_n_o,
treq_db_info,
treq_msg_len,
treq_msg_seg,
treq_mbox,
treq_letter
srio_wr_en,
srio_rd_en,
srio_wr_data,
srio_rd_data,
fft2_calc_finish,
cpu_reset_n
);
// System Interface
input sys_clk;
input lnk_reset_n;
// Target Request Interface
// Data signals to application interface
input [0:1] treq_prio_i;
input [0:3] treq_ftype_i;
input [0:7] treq_dest_id_i;
input [0:7] treq_src_id_i;
input [0:7] treq_tid_i;
input [0:3] treq_ttype_i;
input [0:33] treq_addr_i; /**/
input [0:7] treq_byte_en_n_i;
input [0:8] treq_byte_count_i;
input [0:63] treq_data_i;
// Target Req control signals
input treq_sof_n_i;
input treq_eof_n_i;
input treq_vld_n_i;
output treq_rdy_n_o;
// Target Response Interface
// Data signals to application interface
input [0:15] treq_db_info;
input [0:3] treq_msg_len;
input [0:3] treq_msg_seg;
input [0:5] treq_mbox;
input [0:1] treq_letter;
output [0:1] tresp_prio_o;
output [0:3] tresp_ftype_o;
output [0:7] tresp_dest_id_o;
output [0:3] tresp_ttype_o;
output [0:3] tresp_status_o;
output [0:7] tresp_tid_o;
output [0:63] tresp_data_o;
output [0:3] tresp_msg_seg;
output [0:1] tresp_mbox;
output [0:1] tresp_letter;
// Target Response control signals
output tresp_sof_n_o;
output tresp_eof_n_o;
output tresp_vld_n_o;
output tresp_dsc_n_o;
input tresp_rdy_n_i;
input [0:1] tresp_stalls;
/*user*/
output srio_wr_en,
output srio_rd_en,
output [63:0] srio_wr_data,
output [63:0] srio_rd_data,
input fft2_calc_finish,
output cpu_reset_n
// Register and Wire declarations
// Target Response
reg [0:3] tresp_ttype_o;
reg [0:3] tresp_status_o;
reg tresp_sof_n_o;
reg tresp_eof_n_o;
wire tresp_vld_n_o;
reg tresp_rdy_q_n;
reg tresp_sof_q_n;
wire tresp_dsc_n_o;
wire [0:63] tresp_data_o; /*发回数据到主控*/
// Target Request
reg [0:1] treq_prio_q;
reg [0:3] treq_ftype_q;
reg [0:7] treq_src_id_q;
reg [0:7] treq_tid_q;
reg [0:3] treq_ttype_q;
reg [0:63] treq_data_q; /*接收主控发来的数据*/
reg treq_eof_q_n;
wire treq_rdy_n_o;
reg [0:1] treq_letter_q;
reg [0:3] treq_msg_seg_q;
reg [0:1] treq_mbox_q;
// Additional Wire and Registers
reg [0:63] size;
reg [0:21] local_address;
reg [0:5] dword_count;
reg [0:10] state;
reg [0:10] next_state;
reg [0:63] shadow_do;
reg [0:63] next_do;
reg first_valid;
reg init_addr_in_range, next_addr_in_range;
wire tu_error; //target user error
wire bram_select;
wire rd_en;
wire wr_en;
wire size_reg_sel;
wire [0:63] bram_do;
reg [0:1] stall_cnt;
wire stall;
reg tresp_vld_n;
reg tresp_vld_q_n_o;
reg [31:0] fpga_status ;
reg cpu_rd_status;
wire cpu_reset;
// Supported address range
// Get rid of the three MSBs
localparam LAD_LOW = 24'h00_0000 >> 3;
localparam LAD_HIGH = 24'h00_7FFC >> 3;
localparam FFT_STATUS_ADDR = 24'h00_8000 >>3;
// State Machine States
`define IDLE 11'h100
`define WRITE 11'h080
`define DB_MSG 11'h200
`define READ_DECODE 11'h040
`define READ_SOF 11'h020
`define READ_NORMAL 11'h010
`define READ_EOF 11'h008
`define READ_SINGLE 11'h004
`define READ_PAUSE 11'h002
`define WRITE_RESP 11'h001
`define DB_MSG_RESP 11'h400
// Misc
assign tu_error = 1'b0;