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有限状态机里的一个实例:
In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).
Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.
题目分析: 大概意思说的是,很多串行通信协议里每个数据字节都有一个起始位和一个停止位来帮助接收端能从一大串比特流里划分出来。常规的方案呢就是 start bit (0)+8 data bits+1 stop bit (1)。空闲时line上是逻辑高。题目意思就是让我们设计有限状态机实现上面这个function,需要注意的一点就是8bit data收到之后,紧跟着要检查stop bit(1), 一直要检车到stop bit,才会跳出这一轮8bit字节的check并开始下一轮。
从下面给出的仿真图可以拿到一个有用信息,done标志位是在start bit (0)+8 data bits+1 stop bit (1)完整接收到会被置1。如果8bit data后面的bit是0,那么done则=0;
我的代码:下面列了两种方法,但是现在还没有优化代码的意识-_- 记得done拉高后清一下
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
reg [1:0] state, next_state;
reg [3:0] cnt;
always@(posedge clk)begin
if(reset)begin
state <= idle;
done <= 0;
cnt <= 3'h0;
end
else
case(state)
idle: begin
done <= 0;
if(in==0)
state <= start;
end
start:begin
if(cnt==3'h7)begin
state <=data;
cnt <= 3'h0;
end
else cnt <= cnt+1'b1;
end
data:
if(in==1)begin
state <= idle;
done <= 1;
end
else state <= stop;
stop: begin
if(in==0)
state <= stop;
else
state <= idle;
end
default: state <= idle;
endcase
end
/*always@(posedge clk)begin
if(reset)
state <= idle;
else state <= next_state;
end
always@(posedge clk)begin
case(state)
idle:begin
cnt <= 0;
done <= 0;
end
start:begin
cnt <= cnt+1'b1;
end
data:begin
cnt <= 0;
if(in)
done <= 1;
else done <= 0;
end
stop:begin
cnt <= 0;
done <= 0;
end
endcase
end
always@(*)begin
case(state)
idle:
next_state = in?idle:start;
start:
next_state = (cnt==3'h7)? data:start;
data:
next_state = in?idle:stop;
stop:
next_state = in?idle:stop;
endcase
end*/
endmodule