DDR standard

tDQSH tDQSL 0.4T 所以，DQS的duty cycle min/max 不能超过40/60.
tQSH (0.43-0.05)T 所以， read 的

 

LPDDR3

4.11.3 Mode Register Write - CA Training Mode

Because CA inputs operate as double data rate, it may be difficult for memory controller to satisfy CA input setup/hold timings at higher frequency. A CA Training mechanism is provided.

4.11.3.1 CA Training Sequence

a) CA Training mode entry: Mode Register Write to MR41

b) CA Training session: Calibrate CA0, CA1, CA2, CA3, CA5, CA6, CA7 and CA8 (see !!! Table 19 on page 67)

c) CA to DQ mapping change: Mode Register Write to MR48

d) Additional CA Training session: Calibrate remaining CA pins (CA4 and CA9) (see !!! Table 21 on page 67)

e) CA Training mode exit: Mode Register Write to MR42

我理解d和e之间，还有CAxR和CAxR#的信号需DDR controller去拉。过程应该是先set CA delay，set CAxR和CAxR#，read from DQ(EVEN 偶数，ODD 奇数)，反复这个过程，最终找到CA delay的Windows，取中间值。

 MR41、MR42和MR48上升沿和下降沿，CA线上不变，所以，不管CA delay是多少，DRAM都可以收到这个Command。

 

上升沿都是偶数的DQ线，下降沿都是奇数的DQ线。共用到16根DQ线。

LPDDR4

器件必须支持multiple operating settings for the die。就是支持OP[0]和OP[1]。默认的OP[0]上是支持低频点的操作的。先在低频点OP[x]上配置training频点OP[y]，前提OP[x]可正常操作，这样保证MRW命令正确。

CA Training(CBT, command bus training)一个事。DQ[6:0]配置memory的Vref(CA)

A status of DQS_t, DQS_c, DQ and DMI are as follows, and DQ ODT state will be followed Frequency

Set Point function except output pins.

- DQS_t[0], DQS_c[0] become input pins for capturing DQ[6:0] levels by its toggling.

- DQ[5:0] become input pins for setting VREF(CA) Level.

- DQ[6] becomes a input pin for setting VREF(CA) Range.

- DQ[7] and DMI[0] become input pins and their input level is Valid level or floating, either way is fine.

- DQ[13:8] become output pins to feedback its capturing value via command bus by CS signal.

- DQS_t[1], DQS_c[1],DMI[1] and DQ[15:14] become output pins or disable, it means that SDRAM may drive to a valid level or left floating.