真值表:
EN | X3 | X2 | X1 | X0 | EF | Y1 | Y0 |
0 | X | X | X | X | 1 | 0 | 0 |
1 | 1 | X | X | X | 0 | 1 | 1 |
1 | 0 | 1 | X | X | 0 | 1 | 0 |
1 | 0 | 0 | 1 | X | 0 | 0 | 1 |
1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
VHDL程序:
library ieee;
use ieee.std_logic_1164.all;
entity encode 4_2 is
port(input:in std_logic_vector(3 downtown 0);
en:in std_logic;
ef:out std_logic;
output:out std_logic_vector(1 downto 0));
end encode 4_2;
architecture encode 4_2_behavior of encode 4_2 is
begin
process(input,en)
begin
if en='0' then
output<="00";
ef<='1';
else
if input(3)='1' then
output<=“11”;
ef<='0';
elsif input(2)='1' then
output<=“10”;
ef<='0';
elsif input(1)='1' then
output<=“01”;
ef<='0';
elsif input(0)='1' then
output<=“00”;
else
output<="00"
ef<='1'
end if;
end if
end process;
end encode 4_2_behavior;