您确定要运行模拟吗?
您的TB代码:
module RAM_IN (pix_val, indx);
input [0:5] indx;
output [31:0] pix_val;
reg [31:0] pix_val;
reg [31:0] in_ram [0:4];
always @ (indx)
pix_val = in_ram [indx];
initial
begin
$readmemb("in_ram.txt", in_ram);
end
endmodule
module tb;
reg [0:5] indx;
wire [31:0] pix_val;
RAM_IN ram_in(pix_val, indx);
initial
begin
indx = 'b0;
$monitor ($realtime, " Read Data = %0b" ,pix_val);
repeat(4)
begin
#10;
indx = indx + 1'd1;
end
$finish;
end
endmodule
使用相同的in_ram.txt。
Questasim:
QuestaSim-64 qverilog 10.4 Compiler 2014.12 Dec 2 2014
Start time: 18:27:01 on May 10,2016
qverilog m