1.编写如下源代码
`timescale 1ns / 1ps
module top(
input clk,
input rst,
output test_clk,
input [1:0] switch,
output [3:0] r,g,b,
output hs,vs
);
wire clk40M, clk25M;
// rst = 0
assign test_clk = (rst) ? clk40M : clk25M;
// 100MHz x10 --> 1000MHz
// 800~1600,
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(25), // 40M
.CLKOUT1_DIVIDE(40), // 25M
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),