matlab test bench,Set Up Cosimulation Test Bench

Specify HDL Signal/Port and Module Paths for MATLAB Test Bench Cosimulation

HDL Verifier™ software has specific requirements for

specifying HDL design hierarchy, the syntax of which is described

in the following sections: one for Verilog® at the top level,

and one for VHDL® at the top level. Do not use a file name hierarchy

in place of the design hierarchy name.

The rules stated in this section apply to signal/port and module

path specifications for MATLAB cosimulation sessions. Other specifications

may work but the HDL Verifier software does not officially

recognize nor support them.

In the following example:

matlabtb u_osc_filter -mfunc oscfilter

u_osc_filter is the top-level component.

If you specify a subcomponent, you must follow valid module path specifications

for MATLAB cosimulation sessions.

Path Specifications for MATLAB Link Sessions with Verilog Top Level

The path specification must start with a top-level

module name.

The path specification can include "." or "/" path

delimiters, but it cannot include mixed delimiters.

The leaf module or signal must match the HDL language

of the top-level module.

The following examples show valid signal and module path specifications:

top.port_or_sig

/top/sub/port_or_sig

top

top/sub

top.sub1.sub2

The following examples show invalid signal

and module path specifications:

top.sub/port_or_sig

Why this specification is invalid: You

cannot use mixed delimiters.

:sub:port_or_sig

:

:sub

Why this specification is invalid: When

you use VHDL-specific delimiters you limit the interoperability

with paths when moving between HDL simulators and between VHDL and Verilog.

Path Specifications for MATLAB Link Sessions with VHDL Top Level

The path specification can include the top-level module

name, but you do not have to include it.

The path specification can include "." or "/" path

delimiters, but it cannot include mixed delimiters.

The leaf module or signal must match the HDL language

of the top-level module.

The following examples show valid signal and module path specifications:

top.port_or_sig

/sub/port_or_sig

top

top/sub

top.sub1.sub2

The following examples show invalid signal

and module path specifications:

top.sub/port_or_sig

Why this specification is invalid: You

cannot use mixed delimiters.

:sub:port_or_sig

:

:sub

Why this specification is invalid:When

you use VHDL-specific delimiters you limit the interoperability

with paths when moving between HDL simulators and between VHDL and Verilog.