[sva]在设计的RTL中加入assert

1. Include

/* File name : bus_arbiter.sv*/
// Design module
module bus_arbiter (
input logic clk,
input logic rst,
input logic [7:0] a,
input logic a_vld,
input logic [7:0] b,
input logic b_vld,
output logic [7:0] c);

logic [1:0] arb_sig;
logic [31:0] a_cnt;
logic [31:0] b_cnt;
logic [3:0] current_state;

// ... design code goes here

// place this at the end, right before endmodule
`include "bus_arb_assertions.svh"

endmodule: bus_arbiter