modelsim vlog option

The vlog command is used to invoke VLOG, the Model Technology Verilog compiler. Use vlog to compile Verilog source code into a specified working library (or to the work library by default).

This command may be invoked from within ModelSim or from the operating system command prompt. This command may also be invoked during simulation.

Syntax

vlog
[-93] [-help] [-compat] [-compile_uselibs[=<directory_name>]]
[-debugCellOpt] [+define+<macro_name>[=<macro_text>]] [+delay_mode_distributed] [+delay_mode_path] [+delay_mode_unit] [+delay_mode_zero] [-f ] [-fast[=<secondary_name>] [+acc[=][+[.]]]] [-forcecode]
[-hazards] [+incdir+] [-incr] [-L ] [-Lf ] [+libext+] [+librescan] [-line ] [lint] [+mindelays] [+maxdelays] [+nocheckALL] [+nocheckCLUP] [+nocheckDNET] [+nocheckOPRD] [+nocheckSUDP] [nodebug[=ports | =pli]] [noincr] [+nolibcell] [-nolock] [-nologo] [+nowarn] [-O0 | -O1 | -O4 | -O5] [+opt+[.]] [-quiet] [-R ] [-refresh] [source] [+typdelays] [-u]
[-v <library_file>] [-version] [-work <library_name>]
[-y <library_directory>]

Arguments

-93
Specifies that the VHDL interface to Verilog modules shall use VHDL 1076-1993 extended identifiers to preserve case in Verilog identifiers that contain uppercase letters.

-help
Displays the command’s options and arguments. Optional.

-compat
The Verilog language does not specify the order that a simulator must execute simultaneous events; however, some models depend on the event ordering of the simulator that the model was developed on. The -compat switch disables optimizations that result in an event order that is different from some other widely used Verilog simulators. You can also use the hazards switch to help find code that depends on a specific event ordering.

-compile_uselibs[=<directory_name>]
Locates source files specified in a uselib directive (see "Verilog-XL uselib compiler directive" ), compiles those files into automatically created libraries, and updates the modelsim.ini file with the logical mappings to the new libraries. Optional. If a directory_name is not specified, ModelSim uses the name specified in the MTI_USELIB_DIR environment variable. If that variable is not set, ModelSim creates a directory named “mti_uselibs” in the current working directory.

-debugCellOpt
Produces Transcript window output that identifies why certain cells within the design were not optimized. Used only when compiling gate-level Verilog libraries with -fast (see below). Optional.

+define+<macro_name>[=<macro_text>]
Same as compiler directive: `define macro_name macro_text. Optional.

+delay_mode_distributed
Uses structural delays and ignore path delays. Optional.

+delay_mode_path
Sets structural delays to zero and use path delays. Optional.

+delay_mode_unit
Sets non-zero structural delays to one. Optional.

+delay_mode_zero
Sets structural delays to zero. Optional.

-f
Specifies a file with more command line arguments. Allows complex arguments to be reused without retyping. Optional.

-fast[=<secondary_name>] [+acc[=][+[.]]]
Increases simulation speed by allowing parameter propagation and global optimizations. Optional. To use this parameter, you must compile the source code for your entire design in a single invocation of the compiler. The following options are available:

=secondary_name
Allows you to specify a different secondary name for the optimized code. The compiler automatically assigns a secondary name to distinguish optimized code from unoptimized code that may exist in the same library. The default secondary name for optimized code is “fast”; the default secondary name for unoptimized code is “verilog”.

+acc[=][+[.]]
Allows you to maintain design object visibility. Note that using this option may reduce simulation speed. The +acc syntax is as follows:

 <spec> is one or more of the following characters:

r Enable access to registers (including memories, integer, time, and real types).

n Enable access to nets.

b Enable access to bits of vector nets. This is necessary for PLI applications that require handles to individual bits of vector nets. Also, some user interface commands require this access if you need to operate on net bits.

p Enable access to ports. This disables the module inlining optimization, and is necessary only if you have PLI applications that require access to port handles.

c Enable access to library cells. By default any Verilog module bracketed with a `celldefine / `endcelldefine may be optimized, and debug and PLI access may be limited. This option keeps module cell visibility.

 If <spec> is omitted, access is enabled for all objects.

is a module name, optionally followed by “.” to indicate all children of the module. Multiple modules are allowed, with each separated by a “+”. If no modules are specified, then all modules are affected.

Note: Please see additional discussion about -fast in “Compiling for faster performance” in the Verilog simulation chapter. Also, see below for +nocheck arguments that increase -fast optimizations.
-forcecode
Forces code generation for optimized inline modules when using the -fast switch. Optional. Use only in conjunction with the -fast switch. By default, code is not generated for inline modules when the -fast switch is used.

-hazards
Enables the run-time hazard checking code. Optional.

+incdir+
Searches directory for files included with the `include filename compiler directive. Optional.

-incr
Performs an incremental compile. Optional. Compiles only code that has changed, or if compile options change.

-L
Searches the specified library for precompiled modules. Optional.

This argument can be used in tandem with -fast (see above) when you need to optimize pre-compiled modules for which you don’t have source code. The library search options you specify here must also be specified when you run the vsim command.

-Lf
Same as -L but the specified library is searched before any 'uselib directives. (See “Library usage” and “Verilog-XL `uselib compiler directive” for more information). Optional.

+libext+
Specifies the suffix of files in the library directory. Multiple suffixes may be used, for example: +libext+.v+.u. Optional.

+librescan
Scans libraries in command-line order for all unresolved modules. Optional.

-line
Starts the compiler on the specified line in the Verilog source file. Optional. By default, the compiler starts at the beginning of the file.

lint
Instructs ModelSim to perform three lint-style checks: 1) warn when Module ports are NULL; 2) warn when assigning to an input port; 3) warn when referencing undeclared variables/nets in an instantiation. The warnings are reported as WARNING[8]. Can also be enabled using the Show_Lint variable in the modelsim.ini file.

+mindelays
Selects minimum timing from Verilog min:typ:max expressions. Optional.

+maxdelays
Selects maximum timing from Verilog min:typ:max expressions. Optional.

+nocheckALL
Enables all +nocheck arguments described below. Optional. Argument has an effect only when compiling gate-level cell libraries with -fast (see above). The +nocheck switches increase the optimizations of -fast.

+nocheckCLUP
Allows connectivity loops in a cell to be optimized. Optional. Argument has an effect only when compiling gate-level cell libraries with -fast (see above).

+nocheckDNET
Allows both the port and the delayed port (created for negative setup/hold) to be used in the functional section of the cell. Optional. Argument has an effect only when compiling gate-level cell libraries with -fast (see above).

+nocheckOPRD
Allows an output port to be read internally by the cell. Optional. Argument has an effect only when compiling gate-level cell libraries with -fast (see above). Note that if the value read is the only value contributed to the output by the cell, and if there’s a driver on the net outside the cell, the value read will not reflect the resolved value.

+nocheckSUDP
Allows a sequential UDP to drive another sequential UDP. Optional. Argument has an effect only when compiling gate-level cell libraries with -fast (see above).

nodebug[=ports | =pli]
Hides the internal data of the compiled design unit. Optional. The design unit’s source code, internal structure, registers, nets, etc. will not display in ModelSim’s windows. In addition, none of the hidden objects may be accessed through the Dataflow window or with commands. This also means that you cannot set breakpoints or single step within this code. Don’t compile with this switch until you’re done debugging.

Note that this is not a speed switch like the “nodebug” option on many other products. Use the -fast switch to increase simulation speed.

The optional =ports switch hides the ports for the lower levels of your design; it should be used only to compile the lower levels of the design. If you hide the ports of the top level you will not be able to simulate the design.

The optional =pli switch prevents the use of pli functions to interrogate individual modules for information; this switch may be used at any level of the design. Combine both switches with =ports+pli or =pli+ports.

Note: -nodebug provides protection for proprietary model information. The Verilog 'protect compiler directive provides similar protection, but uses a Cadence encryption algorithm that is unavailable to Model Technology.
See additional discussion in “Source code security and -nodebug” .

noincr
Disables incremental compile previously turned on with -incr. Optional.

+nolibcell
Do not automatically define library modules as cells. Optional.

-nolock
Overrides the library lock file. The lock file prevents mulitple users from concurrently accessing the same library. If you are a single user, disabling the lock file should not present a problem. Optional. Default is locked.

-nologo
Disables the startup banner. Optional.

+nowarn
Disables warning messages in the category specified by . Optional. Warnings that can be disabled include the name in square brackets in the warning message. For example the code for decay warnings is DECAY, so use +nowarnDECAY to disable them.

-O0 | -O1 | -O4 | -O5
Lower the optimization to a minimum with -O0 (capital oh zero). Optional. Use this to work around bugs, increase your debugging visibility on a specific cell, or when you want to place breakpoints on source lines that have been optimized out.

Enable PE-level optimization with -O1. Optional.

Enable standard SE optimizations with -O4. Default.

Enable maximum optimization with -O5. Optional. Use caution with this switch. We recommend use of this switch with large sequential blocks only; other uses may significantly increase compile times. Also, before using -O5 with -fast (described above), try using both switches independently to make sure the optimized design behaves the same as the original version.

+opt+[.]
Generates optimized code for designs that have been previously compiled unoptimized (without the -fast option; see above). Optional. The specification is the name of the top-level design module, and , which is optional, is the library in which it resides. By default, the top-level module is searched for in the work library. If the design has multiple top-level modules, then provide the names in a list separated by plus signs. For example,

vlog +opt+testbench+globals

The optimizations performed by +opt are identical to those performed by -fast. The only difference is that +opt does not need to compile the source code; instead it loads the design units from the libraries and regenerates optimized code for them. If the design units reside in multiple libraries, then it may be necessary to specify the appropriate library search options to the compiler in addition to the +opt option.

Any options that are appropriate with -fast are also appropriate with +opt. Specifically, use the +acc option to enable PLI access, and use the -L and -Lf options to specify the libraries to be searched. The -fast option is also allowed with +opt, but it is only useful if you want to specify the secondary name used for the optimized design units
(-fast=).

-quiet
Disables ‘loading’ messages. Optional.

-R
Causes VSIM to be invoked on the top-level Verilog modules immediately following compilation. VSIM is invoked with the arguments specified by (any arguments available for vsim).

-refresh
Regenerates a library image. Optional. By default, the work library is updated; use -work <library_name> to update a different library. See vlog examples for more information.

source
Displays the associated line of source code before each error message that is generated during compilation. Optional; by default, only the error message is displayed.

+typdelays
Selects typical timing from Verilog min:typ:max expressions. Optional. Default.

-u
Converts regular Verilog identifiers to uppercase. Allows case insensitivity for module names. Optional.

-v <library_file>
Specifies the Verilog source library file to search for undefined modules. Optional. After all explicit filenames on the vlog command line have been processed, the compiler uses the -v option to find and compile any modules that were referenced but not yet defined. See additional discussion in the examples.

-version
Returns the version of the compiler as used by the licensing tools, such as “Model Technology ModelSim SE vlog 5.5 Compiler 2000.01 Jan 28 2000”.

-work <library_name>
Specifies a logical name or pathname of a library that is to be mapped to the logical library work. Optional; by default, the compiled design units are added to the work library. The specified pathname overrides the pathname specified for work in the project file.

-y <library_directory>
Specifies the Verilog source library directory to search for undefined modules. Optional. After all explicit filenames on the vlog command line have been processed, the compiler uses the -y option to find and compile any modules that were referenced but not yet defined. You will need to specify a file suffix by using -y in conjunction with the +libext+ option if your filenames differ from your module names. See additional discussion in the examples.

Specifies the name of the Verilog source code file to compile. One filename is required. Multiple filenames can be entered separated by spaces. Wildcards can be used.

Examples

vlog example.vlg
Compiles the Verilog source code contained in the file example.vlg.

vlog -nodebug example.v
Hides the internal data of example.v. Models compiled with -nodebug cannot use any of the ModelSim debugging features; any subsequent user will not be able to see into the model.

vlog -nodebug=ports level3.v level2.v
vlog -nodebug top.v
The first line compiles and hides the internal data, plus the ports, of the lower-level design units, level3.v and level2.v. The second line compiles the top-level unit, top.v, without hiding the ports. It is important to compile the top level without =ports because top-level ports must be visible for simulation.

vlog -nodebug=ports+pli level3.v level2.v
vlog -nodebug=pli top.v
The first command hides the internal data, and ports of the design units, level3.v and level2.v. In addition it prevents the use of pli functions to interrogate the compiled modules for information (either =ports+pli or =pli+ports works fine for this command). The second line compiles the top-level unit without hiding the ports but restricts the use of pli functions as well.

Note that the =pli switch may be used at any level of the design but =ports should only be used on lower levels since you can’t simulate without visible top-level ports.

See “Source code security and -nodebug” for more details.

vlog -fast cpu_rtl.v
Compiles all modules in cpu_rtl.v using global optimizations. Assuming your toplevel module is named testbench, you would simulate the design as follows:

vsim -c testbench
vlog -fast=opt1 cpu_rtl.v
Compiles all modules in cpu_rtl.v using global optimizations, and assigns the secondary name “opt1” to the optimized modules.

vlog -fast +acc=rn cpu_rtl.v
Compiles cpu_rtl.v using global optimizations, but enables net and register access in all modules in the design.

Note: Please see additional discussion about -fast in “Compiling for faster performance” in the Verilog simulation chapter.
vlog top.v -v und1
After compiling top.v, vlog will scan the file und1 for modules or primitives referenced but undefined in top.v. Only referenced definitions will be compiled.

vlog top.v +libext+.v+.u -y vlog_lib
After compiling top.v, vlog will scan the vlog_lib library for files with modules with the same name as primitives referenced, but undefined in top.v. The use of +libext+.v+.u implies filenames with a .v or .u suffix (any combination of suffixes may be used). Only referenced definitions will be compiled.

vlog -work mylib -refresh
The work option specifies mylib as the library to regenerate. refresh rebuilds the library image without using source code, allowing models delivered as compiled libraries without source code to be rebuilt for a specific release of ModelSim (4.6 and later only).

If your library contains VHDL design units be sure to regenerate the library with the vcom command using the refresh option as well. See “Regenerating your design libraries” for more information.

vlog module1.v -u -O0 -incr
The incr option determines whether or not the module source or compile options have changed as module1 is parsed. If no change is found, the code generation phase is skipped. Differences in compile options are determined by comparing the compiler options stored in the _info file with the compiler options given. They must match exactly.

-mfcu

vlog -mfcu -sv ../head/head.v  ../sv/packet.sv  ../sv/generator.sv    ………

上面语句中-sv 可以省略不写，但是-mfcu必须写，在questasim Transcri 命令栏下打上 vlog -help 会弹出很多的帮助信息，这些帮助信息里面有-mfcu的介绍，意思是 -mfcu 后面需要跟上所有需要编译的文件，且不同文件之间的宏定义是可见的。

# -mfcu[=macro] Multi-file compilation unit, all files in command line make up a compilation unit.

#The =macro modifier only enables the visibility of macro definitions across different files.

#The default is to have each file be a separate compilation unit (-sfcu mode).

---

vsim -batch -voptargs="+acc=npr" -lib qrun.out/work -do " run -all; exit" -statslog qrun.out/stats_log qrun_opt -appendlog -l qrun.log