verilog delay mode

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Delay modes
Verilog models may contain both distributed delays and path delays. The delays on primitives, UDPs, and continuous assignments are the distributed delays, whereas the port-to-port delays specified in specify blocks are the path delays. These delays interact to determine the actual delay observed. Most Verilog cells use path delays exclusively, with the distributed delays set to zero. For example,

module and2(y, a, b);
	input a, b;
	output y; 
	and(y, a, b); 
	specify
		(a => y) = 5;
		(b => y) = 5;
	endspecify
endmodule 

In the above two-input “and” gate cell, the distributed delay for the “and” primitive is zero, and the actual delays observed on the module ports are taken from the path delays. This is typical for most cells, but a complex cell may require non-zero distributed delays to work properly. Even so, these delays are usually small enough that the path delays take priority over the distributed delays. The rule is that if a module contains both path delays and distributed delays, then the larger of the two delays for each path shall be used (as defined by the IEEE Std 1364). This is the default behavior, but you can specify alternate delay modes with compiler directives and options. These options and directives are compatible with Verilog-XL. Compiler delay mode options take precedence over delay mode directives in the source code.

Distributed delay mode
In distributed delay mode the specify path delays are ignored in favor of the distributed delays. Select this delay mode with the +delay_mode_distributed compiler option or the `delay_mode_distributed compiler directive.

Path delay mode
In path delay mode the distributed delays are set to zero in any module that contains a path delay. Select this delay mode with the +delay_mode_path compiler option or the `delay_mode_path compiler directive.

Unit delay mode
In unit delay mode the distributed delays are set to one (the unit is the time_unit specified in the timescale directive), and the specify path delays and timing constraints are ignored. Select this delay mode with the +delay_mode_unit compiler option or the delay_mode_unit compiler directive.

Zero delay mode
In zero delay mode the distributed delays are set to zero, and the specify path delays and timing constraints are ignored. Select this delay mode with the +delay_mode_zero compiler option or the delay_mode_zero compiler directive.