左移寄存器vhdl_移位寄存器VHDL描述.doc

移位寄存器VHDL描述

移位寄存器的VHDL描述

8位移位寄存器

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY shifter IS

PORT (

data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);--输入的数据

n: IN STD_LOGIC_VECTOR(2 DOWNTO 0);--移位的数量

dir: IN STD_LOGIC--移动的方向 0:左 1:右

kind: IN STD_LOGIC_VECTOR(1 DOWNTO 0)；--移动类型 00:算术移 01:逻辑移 10:循环移

clock: IN BIT；--手动时钟PULSE

data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--移位的结果

);

END shifter;ARCHITECTURE behav of shifter IS

BEGIN

PROCESS (data_in, n, dir, kind)

VARIABLE x,y : STD_LOGIC_VECTOR(7 DOWNTO 0);

VARIABLE ctrl0,ctrl1,ctrl2 : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

IF (clock’EVENT AND clock = ‘1’)THEN--产生控制向量ctrl

ctrl0 := n(0) & dir & kind(1) & kind(0);

ctrl1 := n(1) & dir & kind(1) & kind(0);

ctrl2 :=