axi时序图_Zynq-PL中创建AXI Master接口IP及AXI4-Lite总线主从读写时序测试(转）

`timescale 1ns /1psmoduleTop_AXI4_Lite_Interfce_Demo

#(parameter C_AXI_START_DATA_VALUE = 32'hAA000000,

parameter C_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,

parameter integer C_AXI_ADDR_WIDTH = 32,parameter integer C_AXI_DATA_WIDTH = 32,parameter integer C_AXI_TRANSACTIONS_NUM = 4)

(inputaxi_ACLK,inputaxi_ARESETn,inputapp_TXn,outputstate_err,outputstate_done

);wire w_err; //状态指示，异常

wire w_txn_done; //状态指示，发送完毕

assign state_err =w_err;assign state_done =w_txn_done;wire [C_AXI_ADDR_WIDTH-1 : 0] axi_AWADDR; //AXI总线信号：AWADDR

wire [2 : 0] axi_AWPROT; //AXI总线信号：AWPROT

wire axi_AWVALID; //AXI总线信号：AWVALID

wire axi_AWREADY; //AXI总线信号：AWREAD

wire [C_AXI_DATA_WIDTH-1 : 0] axi_WDATA; //AXI总线信号：WDATA

wire [C_AXI_DATA_WIDTH/8-1 : 0] axi_WSTRB; //AXI总线信号：WSTRB

wire axi_WVALID; //AXI总线信号：WVALID

wire axi_WREADY; //AXI总线信号：WREADY

wire [1 : 0] axi_BRESP; //AXI总线信号：BRESP

wire axi_BVALID; //AXI总线信号：BVALID

wire axi_BREADY; //AXI总线信号：BREADY

wire [C_AXI_ADDR_WIDTH-1 : 0] axi_ARADDR; //AXI总线信号：ARADDR

wire [2 : 0] axi_ARPROT; //AXI总线信号：ARPROT

wire axi_ARVALID; //AXI总线信号：ARVALID

wire axi_ARREADY; //AXI总线信号：ARREADY

wire [C_AXI_DATA_WIDTH-1 : 0] axi_RDATA; //AXI总线信号：RDATA

wire [1 : 0] axi_RRESP; //AXI总线信号：RRESP

wire axi_RVAILD; //AXI总线信号：RVAILD

wire axi_RREADY; //AXI总线信号：RREADYaxi_ip_master_v1_0 #

(

.C_M00_AXI_START_DATA_VALUE(C_AXI_START_DATA_VALUE),

.C_M00_AXI_TARGET_SLAVE_BASE_ADDR(C_AXI_TARGET_SLAVE_BASE_ADDR),

.C_M00_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),

.C_M00_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),

.C_M00_AXI_TRANSACTIONS_NUM(C_AXI_TRANSACTIONS_NUM)

) Ut1 (//-- AXI4-Lite Global ----------------------------------------------.m00_axi_aclk(axi_ACLK),

.m00_axi_aresetn(axi_ARESETn),//------------------------------------------------------------------.m00_axi_init_axi_txn(app_TXn),

.m00_axi_error(w_err),

.m00_axi_txn_done(w_txn_done),//--- AXI4-Lite Write Address Channel ------------------------------.m00_axi_awaddr(axi_AWADDR),

.m00_axi_awprot(axi_AWPROT),

.m00_axi_awvalid(axi_AWVALID),

.m00_axi_awready(axi_AWREADY),//--- AXI4-Lite Write data Channel ------------------------------.m00_axi_wdata(axi_WDATA),

.m00_axi_wstrb(axi_WSTRB),

.m00_axi_wvalid(axi_WVALID),

.m00_axi_wready(axi_WREADY),//--- AXI4-Lite Write response Channel ------------------------------.m00_axi_bresp(axi_BRESP),

.m00_axi_bvalid(axi_BVALID),

.m00_axi_bready(axi_BREADY),//--- AXI4-Lite Read Address Channel ------------------------------.m00_axi_araddr(axi_ARADDR),

.m00_axi_arprot(axi_ARPROT),

.m00_axi_arvalid(axi_ARVALID),

.m00_axi_arready(axi_ARREADY),//--- AXI4-Lite Read Data Channel ------------------------------.m00_axi_rdata(axi_RDATA),

.m00_axi_rresp(axi_RRESP),

.m00_axi_rvalid(axi_RVAILD),

.m00_axi_rready(axi_RREADY)

);

axi_ip_slave_v1_0 #

(

.C_S00_AXI_DATA_WIDTH(C_AXI_ADDR_WIDTH),

.C_S00_AXI_ADDR_WIDTH(7)

) Ut2 (//-- AXI4-Lite Global ----------------------------------------------.s00_axi_aclk(axi_ACLK),

.s00_axi_aresetn(axi_ARESETn),//--- AXI4-Lite Write Address Channel ------------------------------.s00_axi_awaddr(axi_AWADDR[6:0]), //注意：只有段地址！！！！！,做的axi_slave_ip的地址位宽为7，寄存器个数为32.s00_axi_awprot(axi_AWPROT),

.s00_axi_awvalid(axi_AWVALID),

.s00_axi_awready(axi_AWREADY),//--- AXI4-Lite Write data Channel --------------------------------.s00_axi_wdata(axi_WDATA),

.s00_axi_wstrb(axi_WSTRB),

.s00_axi_wvalid(axi_WVALID),

.s00_axi_wready(axi_WREADY),//--- AXI4-Lite Write response Channel ------------------------------.s00_axi_bresp(axi_BRESP),

.s00_axi_bvalid(axi_BVALID),

.s00_axi_bready(axi_BREADY),//--- AXI4-Lite Read Address Channel ------------------------------.s00_axi_araddr(axi_ARADDR),

.s00_axi_arprot(axi_ARPROT),

.s00_axi_arvalid(axi_ARVALID),

.s00_axi_arready(axi_ARREADY),//--- AXI4-Lite Read Data Channel ------------------------------.s00_axi_rdata(axi_RDATA),

.s00_axi_rresp(axi_RRESP),

.s00_axi_rvalid(axi_RVAILD),

.s00_axi_rready(axi_RREADY)

);endmodule附录2：底层模块MASTER 顶层源代码：

`timescale1 ns / 1psmoduleaxi_ip_master_v1_0 #

(//Users to add parameters here//User parameters ends//Do not modify the parameters beyond this line//Parameters of Axi Master Bus Interface M00_AXI

parameter C_M00_AXI_START_DATA_VALUE = 32'hAA000000,

parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,

parameter integer C_M00_AXI_ADDR_WIDTH = 32,parameter integer C_M00_AXI_DATA_WIDTH = 32,parameter integer C_M00_AXI_TRANSACTIONS_NUM = 4)

(//Users to add ports here//User ports ends//Do not modify the ports beyond this line//Ports of Axi Master Bus Interface M00_AXI

input wirem00_axi_init_axi_txn,output wirem00_axi_error,output wirem00_axi_txn_done,input wirem00_axi_aclk,input wirem00_axi_aresetn,output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,output wire [2 : 0] m00_axi_awprot,output wirem00_axi_awvalid,input wirem00_axi_awready,output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,output wirem00_axi_wvalid,input wirem00_axi_wready,input wire [1 : 0] m00_axi_bresp,input wirem00_axi_bvalid,output wirem00_axi_bready,output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,output wire [2 : 0] m00_axi_arprot,output wirem00_axi_arvalid,input wirem00_axi_arready,input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,input wire [1 : 0] m00_axi_rresp,input wirem00_axi_rvalid,output wirem00_axi_rready

);//Instantiation of Axi Bus Interface M00_AXI

axi_ip_master_v1_0_M00_AXI # (

.C_M_START_DATA_VALUE(C_M00_AXI_START_DATA_VALUE),

.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),

.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),

.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),

.C_M_TRANSACTIONS_NUM(C_M00_AXI_TRANSACTIONS_NUM)

) axi_ip_master_v1_0_M00_AXI_inst (

.INIT_AXI_TXN(m00_axi_init_axi_txn),

.ERROR(m00_axi_error),

.TXN_DONE(m00_axi_txn_done),

.M_AXI_ACLK(m00_axi_aclk),

.M_AXI_ARESETN(m00_axi_aresetn),

.M_AXI_AWADDR(m00_axi_awaddr),

.M_AXI_AWPROT(m00_axi_awprot),

.M_AXI_AWVALID(m00_axi_awvalid),

.M_AXI_AWREADY(m00_axi_awready),

.M_AXI_WDATA(m00_axi_wdata),

.M_AXI_WSTRB(m00_axi_wstrb),

.M_AXI_WVALID(m00_axi_wvalid),

.M_AXI_WREADY(m00_axi_wready),

.M_AXI_BRESP(m00_axi_bresp),

.M_AXI_BVALID(m00_axi_bvalid),

.M_AXI_BREADY(m00_axi_bready),

.M_AXI_ARADDR(m00_axi_araddr),

.M_AXI_ARPROT(m00_axi_arprot),

.M_AXI_ARVALID(m00_axi_arvalid),

.M_AXI_ARREADY(m00_axi_arready),

.M_AXI_RDATA(m00_axi_rdata),

.M_AXI_RRESP(m00_axi_rresp),

.M_AXI_RVALID(m00_axi_rvalid),

.M_AXI_RREADY(m00_axi_rready)

);//Add user logic here//User logic ends

endmodule附录3：底层模块MASTER 底层源代码：

`timescale1 ns / 1psmoduleaxi_ip_master_v1_0_M00_AXI #

(//Users to add parameters here//User parameters ends//Do not modify the parameters beyond this line//The master will start generating data from the C_M_START_DATA_VALUE value

parameter C_M_START_DATA_VALUE = 32'hAA000000,

//The master requires a target slave base address.//The master will initiate read and write transactions on the slave with base address specified here as a parameter.

parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,

//Width of M_AXI address bus.//The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.

parameter integer C_M_AXI_ADDR_WIDTH = 32,//Width of M_AXI data bus.//The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH

parameter integer C_M_AXI_DATA_WIDTH = 32,//Transaction number is the number of write//and read transactions the master will perform as a part of this example memory test.

parameter integer C_M_TRANSACTIONS_NUM = 4)

(//Users to add ports here//User ports ends//Do not modify the ports beyond this line//Initiate AXI transactions

input wireINIT_AXI_TXN,//Asserts when ERROR is detected

output regERROR,//Asserts when AXI transactions is complete

output wireTXN_DONE,//AXI clock signal

input wireM_AXI_ACLK,//AXI active low reset signal

input wireM_AXI_ARESETN,//Master Interface Write Address Channel ports. Write address (issued by master)

output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,//Write channel Protection type.//This signal indicates the privilege and security level of the transaction,//and whether the transaction is a data access or an instruction access.

output wire [2 : 0] M_AXI_AWPROT,//Write address valid.//This signal indicates that the master signaling valid write address and control information.

output wireM_AXI_AWVALID,//Write address ready.//This signal indicates that the slave is ready to accept an address and associated control signals.

input wireM_AXI_AWREADY,//Master Interface Write Data Channel ports. Write data (issued by master)

output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,//Write strobes.//This signal indicates which byte lanes hold valid data.//There is one write strobe bit for each eight bits of the write data bus.

output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,//Write valid. This signal indicates that valid write data and strobes are available.

output wireM_AXI_WVALID,//Write ready. This signal indicates that the slave can accept the write data.

input wireM_AXI_WREADY,//Master Interface Write Response Channel ports.//This signal indicates the status of the write transaction.

input wire [1 : 0] M_AXI_BRESP,//Write response valid.//This signal indicates that the channel is signaling a valid write response

input wireM_AXI_BVALID,//Response ready. This signal indicates that the master can accept a write response.

output wireM_AXI_BREADY,//Master Interface Read Address Channel ports. Read address (issued by master)

output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,//Protection type.//This signal indicates the privilege and security level of the transaction,//and whether the transaction is a data access or an instruction access.

output wire [2 : 0] M_AXI_ARPROT,//Read address valid.//This signal indicates that the channel is signaling valid read address and control information.

output wireM_AXI_ARVALID,//Read address ready.//This signal indicates that the slave is ready to accept an address and associated control signals.

input wireM_AXI_ARREADY,//Master Interface Read Data Channel ports. Read data (issued by slave)

input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,//Read response. This signal indicates the status of the read transfer.

input wire [1 : 0] M_AXI_RRESP,//Read valid. This signal indicates that the channel is signaling the required read data.

input wireM_AXI_RVALID,//Read ready. This signal indicates that the master can accept the read data and response information.

output wireM_AXI_RREADY

);//function called clogb2 that returns an integer which has the//value of the ceiling of the log base 2

function integer clogb2 (input integerbit_depth);begin

for(clogb2=0; bit_depth>0; clogb2=clogb2+1)

bit_depth= bit_depth >> 1;end

endfunction

//TRANS_NUM_BITS is the width of the index counter for//number of write or read transaction.

localparam integer TRANS_NUM_BITS = clogb2(C_M_TRANSACTIONS_NUM-1);/