内存颗粒位宽和容量_【推仔说新闻】海力士宣布HBM2E内存 提升50%

虽然说这段时间整体的颗粒市场行情持续下跌,甚至可以说已经跌穿了历史低点,不过从另一个角度来说也算是这几个颗粒大厂为了之前还债了。当然了虽然说市场表现并没有心中预期的那样好,但是各大厂商是不会停下自己研发脚步的。

SK海力士在日前宣布,已经成功研发出新一代DRAM内存HBM2E,这个新研发的内存从其命名规则来看算是与大家熟知的HBM2算是同出一脉,可以看做HBM2的升级版。

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SK海力士官方宣称这个HBM2E拥有业界最高的传输带宽,相比现在的HBM2提升了大约50%,同时容量也翻了一番。

具体来说这个HBM2E内存的每个针脚传输速率为3.6Gbps,搭配1024-bit位宽,其带宽可以达到460GB/s。

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在此之前使用HBM2内存的显卡就有我们熟知的AMD Radeon VII和隔壁老黄家的Titan V了,而其中Radeon VII的显存带宽达到了1TB/s,而就算Titan V的显存带宽也达到了653GB/s,只不过前者的显存位宽为4096-bit后者为3072-bit。

根据官方宣称,这一代的HBM2E采用了TSV硅通孔技术,这个技术可以让HBM2E内存垂直堆叠最多八颗16Gb芯片,实现单颗封装16GB,容量为目前的两倍。

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SK海力士表示,这个新的HBM2E可用于工业4.0、高端GPU显卡、超级计算机、机器学习、AI人工智能等各种尖端领域。

并且该内存颗粒并没有放弃掉HBM的传统优势,它们不用像大家常见的DRAM颗粒那样单独封装、而是可以和GPU等芯片整合封装在一起,不仅可以节省整个PCB的面积,还可以保证传输的速率。

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在推仔看来,虽然说我们看到了HBM2的接任者,不过想想也知道,真等到我们玩家能够享受到这个HBM2E的好处怕还是要很长的时间。毕竟从目前老黄这边来看,他们应该是没有在消费级产品继续使用HBM2的打算了,毕竟全系RTX显卡都没有采用HBM2,而苏妈这边也就出来了个RX 5700系列,Navi还有大把的开发空间。

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select the row; refer to “DDR4 SDRAM Addressing” on datasheet). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.
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