ov5640帧率配置_FPGA配置OV5640摄像头及RGB图像数据采集

1 `timescale 1ns /1ps2

3

4 modulereg_config(5 inputclk,6 inputrst_n,7

8 inputen,9 outputfinish,10

11 inoutsio_d,12 outputsio_c13 );14

15 localparam WR_ID = 8'h78;

16 localparam RW_CTRL = 2'b11;//读

17 wiresio_out_en;18 wiresio_out;19 wiresio_in;20 reg [9-1:0] reg_cnt;21 wireadd_reg_cnt,end_reg_cnt;22 regconfig_flag;23 reg [26-1:0] op_reg_data;24 wirerdy;25 regwr_en;26 reg [16-1:0] reg_addr;27 reg [8-1:0] wr_data;28 regconfig_done;29 reg [ (2-1):0] rw_cnt ;30 wireadd_rw_cnt ;31 wireend_rw_cnt ;32 regrd_en;33 (*DONT_TOUCH = "TRUE"*)wire [8-1:0] rd_data;34 (*DONT_TOUCH = "TRUE"*)wirerd_vld;35

36 sccb_interface sccb_interface(37 .clk (clk) ,38 .rst_n (rst_n) ,39 .wr_en (wr_en) ,40 .rd_en (rd_en),41 .id_addr (WR_ID) ,42 .reg_addr (reg_addr) ,43 .wr_data (wr_data) ,44 .rd_data (rd_data),45 .rd_vld (rd_vld),46 .rdy (rdy) ,47 .sio_c (sio_c) ,48 .sio_out_en(sio_out_en) ,49 .sio_out (sio_out) ,50 .sio_in (sio_in)51 );52

53 assign sio_d = sio_out_en ? sio_out : 1'bz;

54 assign sio_in =sio_d;55

56 always @(posedge clk or negedge rst_n) begin

57 if (rst_n==0) begin

58 rw_cnt <= 0;59 end

60 else if(add_rw_cnt) begin

61 if(end_rw_cnt)62 rw_cnt <= 0;63 else

64 rw_cnt <= rw_cnt+1;65 end

66 end

67 assign add_rw_cnt = (config_flag &&rdy);68 assign end_rw_cnt = add_rw_cnt && rw_cnt == (2)-1 ;//0 write 1 read

69

70 always @(posedge clk or negedge rst_n)begin

71 if(!rst_n)begin

72 reg_cnt <= 0;73 end

74 else if(add_reg_cnt)begin

75 if(end_reg_cnt)76 reg_cnt <= 0;77 else

78 reg_cnt <= reg_cnt + 1;79 end

80 end

81

82 assign add_reg_cnt =end_rw_cnt;83 assign end_reg_cnt = add_reg_cnt && reg_cnt == 261-1;84

85 //配置指令

86 always @(posedge clk or negedge rst_n)begin

87 if(rst_n==1'b0)begin

88 wr_en <= 0;89 reg_addr <= 0;90 wr_data <= 0;91 end

92 else if(add_rw_cnt && rw_cnt == 0)begin

93 wr_en <= op_reg_data[25];94 reg_addr <= op_reg_data[23:8];95 wr_data <= op_reg_data[7:0];96 end

97 else if(end_rw_cnt)begin

98 rd_en <= op_reg_data[24];99 reg_addr <= op_reg_data[23:8];100 end

101 else begin

102 wr_en <= 0;103 rd_en <= 0;104 end

105 end

106

107

108 always @(posedge clk or negedge rst_n)begin

109 if(rst_n==1'b0)begin

110 config_flag <= 0;111 end

112 else if(en && !config_flag && !config_done)begin

113 config_flag <= 1;114 end

115 else if(end_reg_cnt)116 config_flag <= 0;117 end

118

119 always @(posedge clk or negedge rst_n)begin

120 if(rst_n==1'b0)begin

121 config_done <= 0;122 end

123 else if(end_reg_cnt)begin

124 config_done <= 1;125 end

126 end

127

128 assign finish = config_done &&rdy;129

130 always@(*)131 begin//op_reg_data [25] wr [24] rd [23:8] reg_addr [7:0] wr_data

132 case(reg_cnt)133 //15fps VGA YUV output//24MHz input clock, 24MHz PCLK

134 0:op_reg_data= {RW_CTRL, 24'h310311};// system clock from pad, bit[1]

135 1:op_reg_data= {RW_CTRL, 24'h300882};// software reset, bit[7]// delay 5ms

136 2:op_reg_data= {RW_CTRL, 24'h300842};// software power down, bit[6]

137 3:op_reg_data= {RW_CTRL, 24'h310303};// system clock from PLL, bit[1]

138 4:op_reg_data= {RW_CTRL, 24'h3017ff};// FREX, Vsync, HREF, PCLK, D[9:6] output enable

139 5:op_reg_data= {RW_CTRL, 24'h3018ff};// D[5:0], GPIO[1:0] output enable

140 6:op_reg_data= {RW_CTRL, 24'h30341A};// MIPI 10-bit

141 7:op_reg_data= {RW_CTRL, 24'h303713};// PLL root divider, bit[4], PLL pre-divider, bit[3:0]

142 8:op_reg_data= {RW_CTRL, 24'h310801};// PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2] // SCLK root divider, bit[1:0]