AD8400调试记录

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前言

本文记录AD8400数字电位器调试；

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一、AD8400简介

AD8400是单通道、256位、数字控制可变电阻(VR)器件，可实现与机械电位计或可变电阻相同的电子调整功能；

1.功能框图

2.操作时序

二、功能测试

1.测试源码

module top (
	//差分时钟
	input diff_clock_clk_p, 
	input diff_clock_clk_n,
	
	//input clk ,
	input rst_n,  // Asynchronous reset active low
	
	// input trins,
	// input[7:0] trins_data,
	// input trins_rst ,
	//AD8400
	output reg cs ,
	output reg sck,
	output reg sdi,
	//AGND
	output ctrl_o,
	//LED
	output led_o
);

wire clk ;
wire[0:0] trins ;
wire[7:0] trins_data ;

reg[31:0] timer_cnt ;
reg led_reg ;
assign led_o = led_reg ;

reg[3:0] state ;
reg[15:0] sck_cnt ;

reg[4:0] data_bit ;

wire trins_rst ;

//差分转单端
IBUFGDS CLK_U(
	.I(diff_clock_clk_p),
	.IB(diff_clock_clk_n),
	.O(clk)
);

vio_0 vio_inst0 (
  .clk(clk),                // input wire clk
  .probe_out0({ctrl_o,trins_rst}),  // output wire [0 : 0] probe_out0
  .probe_out1(trins),  // output wire [0 : 0] probe_out1
  .probe_out2(trins_data)  // output wire [7 : 0] probe_out2
);

ila_0 ila_inst (
	.clk(clk), // input wire clk
	.probe0({trins,cs,sck,sdi}) // input wire [3:0] probe0
);

//LED计数值
always @(posedge clk or negedge rst_n) begin : led_cnt_task
	if(~rst_n) begin
		timer_cnt <= 0;
	end else begin
		if(timer_cnt==32'd50_000_000-1) timer_cnt<= 0;
		else timer_cnt <= timer_cnt + 1'b1 ;
	end
end
//LED翻转
always @(posedge clk or negedge rst_n) begin : proc_led_reg
	if(~rst_n) begin
		led_reg <= 1;
	end else begin
		if(timer_cnt==32'd50_000_000-1)	led_reg <= ~led_reg;
		else led_reg <= led_reg ;
	end
end

//CS控制
always @(posedge clk or negedge rst_n) begin : proc_cs
	if(~rst_n) begin
		cs <= 1;
	end else begin
		if(state==1) begin
			cs <= 0 ;
		end
		else cs = 1 ;
	end
end

//计数值
always @(posedge clk or negedge rst_n) begin : proc_sck_cnt
	if(~rst_n) begin
		sck_cnt <= 0;
	end else begin
		if(state==1) begin
			if(sck_cnt==999) sck_cnt <= 0 ;
			else sck_cnt <= sck_cnt + 1; 		
		end
		else sck_cnt <= 0;
	end
end

//时钟翻转
always @(posedge clk or negedge rst_n) begin : proc_sck
	if(~rst_n) begin
		sck <= 0;
	end else begin
		if(sck_cnt==499) sck <= ~sck ;
		else if(sck_cnt==999) sck <= ~sck ;
		else sck <= sck;
	end
end

//发送计数
always @(posedge clk or negedge rst_n) begin : proc_data_bit
	if(~rst_n) begin
		data_bit <= 0;
	end else begin
		if(state==1&&sck_cnt==999) data_bit <= data_bit + 1 ;
		else if(state!=1) data_bit = 0 ;
	end
end

//数据线
always @(posedge clk or negedge rst_n) begin : proc_sdi
	if(~rst_n) begin
		sdi <= 0;
	end else begin
		if(state==1) begin
			if(data_bit<2) sdi <= 1'b0;
			else sdi <= trins_data[7-(data_bit-2)];
		end
		else sdi <= 0 ;
	end
end


always @(posedge clk or negedge rst_n) begin : proc_state
	if(~rst_n) begin
		state <= 0;
	end else begin
		case (state)
			0:begin
				if(trins)	state <= 1 ;
				else 		state <= state ;
			end
			1:begin
				if(data_bit==10)	state <= 2 ;
				else state <= state ;
			end
			2:begin
				if(trins_rst) state <= 0;
				else state <= state ;
			end

		endcase
	end
end

endmodule : top

2.仿真结果