Verilog HDL(HDLBits)
Verilog Language Basic
03-Vector-逆转字节
A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.将32位向量视为包含4个字节(位[31:24],[23:16]等)。建立一个电路,该电路将反转4字节字的字节顺序
module top_module(
input [31:0] in,
output [31:0] out );//
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule