Verilog之Vector part select :Vector2

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.

AaaaaaaaBbbbbbbbCcccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa

一个 32 位向量可以被视为包含 4 个字节（位 [31:24]、[23:16] 等）。构建一个将反转 4 字节字的字节顺序的电路。

This operation is often used when the endianness of a piece of data needs to be swapped, for example between little-endian x86 systems and the big-endian formats used in many Internet protocols.

当需要交换一条数据的字节顺序时，通常会使用此操作，例如在小端 x86 系统和许多 Internet 协议中使用的大端格式之间。

Module Declaration

module top_module( 
    input [31:0] in,
    output [31:0] out );

Part-select can be used on both the left side and right side of an assignment.

可用于指定的左侧和右侧。

module top_module( 
    input [31:0] in,
    output [31:0] out );//
    assign out[31:24] = in[ 7: 0];	
	assign out[23:16] = in[15: 8];	
	assign out[15: 8] = in[23:16];	
	assign out[ 7: 0] = in[31:24];	

    // assign out[31:24] = ...;

endmodule

assign out = {in[7-:8],in[15-:8],in[23-:8],in[31-:8]};