HDLBits刷题之2.2.9----Verilog Language----Vectors----More replication

9.More replication

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

题目意思是创建以上的25个一位的输入，将他们进行同或处理，同或处理只需将异或结果取反即可， 代码如下所示：

module top_module (
	input a, b, c, d, e,
	output [24:0] out
);

    assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
	
endmodule