Verilog语言——HDLBits刷题记录(二)

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分类专栏： Verilog 文章标签： fpga开发

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Verilog语言——HDLBits刷题记录(二)

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Verilog语言——HDLBits刷题记录(二)
- Vectors

Vectors

Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc.

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Vertors in more detail

Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.

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Vertor part select

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.
AaaaaaaaBbbbbbbbCcccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa

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Bitwise operators

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

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PS:位操作与逻辑操作的区别

位操作是两个N字节的向量，向量的每一位都进行操作，最终产生一个N字节的输出

逻辑操作时两个N字节的向量，只要判断整体的bool值，产生一字节的输出

Four-input gates

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Vector concatenation operator

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Vector reversal 1

Given an 8-bit input vector [7:0], reverse its bit ordering.

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Replication operator

Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

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