HDLBits:UWaterloo CS450

最近发现HDLBits上面的题目有更新，貌似是滑铁卢大学cs450的题目，准备做一做，把答案整理在下面以供各位参考

1. timer/计时器
   这个题目很好理解，就是当load为1的时候将数据读入并进行倒数，当倒数结束后输出tc为1，需要注意的地方为中间量counter的位数需要和data保持一致。
   

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);
	reg [9:0]counter;
    
    always @(posedge clk) begin
        if(load) begin
           counter <= data;  
        end
        else if(counter!=10'd0) begin
           counter <= counter - 1'd1; 
        end
        else if (counter==10'd0) begin
           counter <= 10'd0; 
        end
    end
    
    assign tc = (counter==10'd0);
    
    
endmodule

2.counter 2bc/计数器
题目挺绕的，没怎么看懂，还好下面的description讲得听明白的，简单来说就是一个下限为0、上限为3的计数器，当train_valid = 1 与 train_taken = 1时计数器值增加，train_valid = 1 and train_taken = 0时计数器值减小，train_valid = 0时计数器值保持不变，自己画了一个有限状态机转移图：

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
    parameter s0=2'd0,s1=2'd1,s2=2'd2,s3=2'd3;
    reg [1:0] current_state,next_state;
    
    always @(*) begin
        case(current_state)
            s0: if(!train_valid) next_state <= s0; //0?
            else if(train_taken) next_state <= s1; //11
            else next_state <= s0; //10
            s1: if(!train_valid) next_state <= s1; //0?
            else if(train_taken) next_state <= s2; //11
            else next_state <= s0; //10
            s2: if(!train_valid) next_state <= s2; //0?
            else if(train_taken) next_state <= s3; //11
            else next_state <= s1; //10
            s3: if(!train_valid) next_state <= s3; //0?
            else if(train_taken) next_state <= s3; //11
            else next_state <= s2; //10
        endcase
    end
    
    always @(posedge clk or posedge areset) begin
        if(areset) current_state <= 2'b01; 
        else current_state <= next_state;
    end
    
    assign state = current_state;

endmodule

3. history shift/历史移位寄存器
   descprition里的大体意思是：当predict_valid = 1，即需要做预测时，predict_taken会作为预测的量从LSB中取出放入predict_history[0];当train_mispredicted=1，即出现错误时，需要将train_history和train_taken连接后再赋给输出predict_history，此外题目明确要求了train_mispredicted的优先级需要高于predict_valid。

module top_module(
    input clk,
    input areset,

    input predict_valid,
    input predict_taken,
    output [31:0] predict_history,

    input train_mispredicted,
    input train_taken,
    input [31:0] train_history
);
    
    always @(posedge clk or posedge areset) begin
        if (areset) begin
           predict_history <= 32'd0; 
        end
        else if(train_mispredicted) begin
            predict_history <= {train_history[30:0],train_taken};
        end
        else if(predict_valid) begin
            predict_history <= {predict_history[30:0],predict_taken};
        end
    end

endmodule