HDLBit练习 Cs450/timer

题目点这

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);
    reg [9:0]data_r;
    

    
    always@(posedge clk)begin
        if(load)begin
            data_r <= data;
        end
   	 	else if(data_r == 10'd0)begin
        data_r <= data_r;
    	end
    	else begin
        data_r<= data_r - 1'b1;
    	end
    end
    


            
    always@(posedge clk)begin
        if(load)begin
            if(data == 10'd0)begin
                tc <= 1;
            end
            else begin
                tc <= 0;
            end
        end
        else if(data_r == 10'd1) begin
            tc <= 1'd1;
        end
        else begin
            tc <=tc;
        end
    end
        
                
    
            

endmodule

下面这个更简单

module top_module(
    input clk, 
    input load, 
    input [9:0] data, 
    output reg tc
);
    reg [9:0]cnt;
 
    always @(posedge clk) begin
        if (load==1'b1)
            cnt <= data;
        else if (cnt==1'b0) 
            cnt <= 1'b0;
        else
            cnt <= cnt-1'b1;
    end
    
    always @(*) begin
        if (cnt==0)
            tc <= 1;
        else
            tc <= 0;
    end            
 
endmodule