全加器设计

设计架构

 

代码编写

module full_addr(
	input in_1,
	input in_2,
	input cin,
	output count,
	output sum
);
wire sum1;
wire count1;
wire count2;
half_addr half_addr0(
	.in_1(in_1),
	.in_2(in_2),
	.sum(sum1),
	.count(count1)
);

half_addr half_addr1(
	.in_1(sum1),
	.in_2(cin),
	.sum(sum),
	.count(count2)
);

assign count=count1 | count2;

endmodule

module half_addr(
	input in_1,
	input in_2,
	output sum,
	output count
);

assign {count,sum}=in_1+in_2;

endmodule

仿真代码

`timescale 1ns/1ns
module tb_full_addr();

	reg in_1;
	reg in_2;
	reg cin;
	wire count;
	wire sum;
	
initial begin
	in_1<=0;
	in_2<=0;
	cin<=0;
end

initial begin
	$timeformat(-9,0,"ns",4);
	$monitor("@time %t:in_1=%b,in_2=%b,cin=%b,count=%b,sum=%b",$time,in_1,in_2,cin,count,sum);
end

always #10 in_1<={$random}%2;
always #10 in_2<={$random}%2;
always #10 cin<={$random}%2;




	
full_addr full_addr(
	.in_1(in_1),
	.in_2(in_2),
	.cin(cin),
	.count(count),
	.sum(sum)
);

endmodule