【数字设计】壁仞科技_笔试面试题目分享

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笔试

壁仞科技的笔试题除了常规的IC设计或者验证的内容外,还包括浮点数的运算,DDR的带宽,PCIE的带宽等与公司业务高度相关的题目,难度比较大,其中的题目包括如下
1.以下四个概念的区分,同时判断以下哪一个DFX是在综合中实现的(以下均不应该在综合中实现)
DFT:Design for Testability
DFM:Design for Manufacturability
DFR:Design for Reliability
DFD:Design for Debug

2.下面哪个FP32数据格式是正确的(符号位,指数位,小数位)
A.1.8.23
B.1.5.26
C.2.8.22
D.2.5.25

正确的 FP32(单精度浮点数)数据格式是选项 C:2.8.22。
在 IEEE 754 浮点数标准中,单精度浮点数(FP32)由三个部分组成:符号位、指数位和小数位。

  1. 符号位:1 位,用于表示数的正负,0 表示正数,1 表示负数。
  2. 指数位:8 位,用于表示数的指数部分,以二进制补码形式表示。
  3. 小数位:23 位,用于表示数的小数部分,以二进制形式表示。

选项 C 中的数据格式是 2.8.22,其中 2 位表示符号位,8 位表示指数位,22 位表示小数位,符合 FP32 的格式要求。

3.对于PCIE gen5 serdes工作在32Gbps线速下,如设计controller数字逻辑频率为1G,请问对于每条lane,data path位宽设计为多少
A.16
B.20
C.32
D.40

PCIE的lane是双通道的,考虑 PCIe Gen5 SerDes 工作在 32 Gbps 线速下,设计 Controller 数字逻辑频率为 1 GHz,对于每条 lane,data path 的位宽应该为:
(32 Gbps / 2) / 1 GHz = 16

4.脚本语言:请写一段Python代码,打开一个文件,扫描每行,如果匹配到biren01,biren02…biren99,则以行号Key,将匹配到的birenxx保存下来

import re

def save_matching_lines(filename):
    target_strings = set()
    with open(filename, 'r') as file:
        for line_num, line in enumerate(file, start=1):
            matches = re.findall(r'biren\d{2}', line)
            if matches:
                target_strings.update(matches)

    with open('matched_strings.txt', 'w') as output_file:
        for line_num, target_string in enumerate(sorted(target_strings), start=1):
            output_file.write(f'Line {line_num}: {target_string}\n')

# 将 'your_file.txt' 替换为您要扫描的文件名
save_matching_lines('your_file.txt')

将代码中的 ‘your_file.txt’ 替换为您要扫描的文件名,然后运行代码。代码将扫描文件的每一行,查找匹配 “biren01” 到 “biren99” 的字符串,并将匹配到的字符串按行号和字母顺序保存在名为 “matched_strings.txt” 的输出文件中。

5.下面的语句分别覆盖了什么行为?
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6.下面的代码有没有错误,如果有,请找出并解释错误原因
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一面

主要是针对于AMBA总线和异步FIFO进行提问

二面

先进制程18-7-5nm对于前端后端的影响

Authors: Dana Crowe & Alec Feinberg 1. Reliability Science 1.1 Introduction 1.2 Reliability Design: “A Stage Gate Approach” 1.3 Design for Reliability Tools 1.4 Reliability Verification 1.5 Analytical Physics 1.6 The Goal Is Customer Satisfaction 2. Understanding Customer Requirements 2.1 Introduction 2.2 Specified and Unspecified Requirements 2.3 Cost of Reliability 2.4 Benchmarking 2.5 Using Failure Modes and Effects Analysis to Meet Customer Requirements 3. Design Assessment Reliability Testing 3.1 Introduction 3.2 Four-Corner HALT Testing 3.3 Design Assessment Reliability Testing at the Hybrid and Component Level 3.4 Summary 4. Design Maturity Testing (DMT) 4.1 Introduction 4.2 Overview of DMT Planning 4.3 DMT Reliability Objectives 4.4 DMT Methods 4.5 Reliability and Sampling Distribution Models 4.6 Sample Size Planning 4.7 Automated Accelerated Test Planning 4.8 DMT Methodology and Guidelines References 5. Screening and Monotoring 5.1 Introduction 5.2 Achieving Reliability Growth in a Screening Program 5.3 Monitoring and Screening Tools 5.4 Highly Accelerated Stress Screening (HASS)Section II: Supporting Stage Gate Authors: Carl Bunis & Peter Ersland 6. Semiconductor Process Reliability 6.1 Introduction 6.2 Overview of Semiconductor Process Reliability Studies in the GaAs Industry 6.3 Wafer Level Reliability Tests 6.4 Summary References 7. Analytical Physics 7.1 Introduction 7.2 Physics of Failure 7.3 Analysis Flow 7.4 Failure Analysis Example 7.5 Analytical Techniques References Section III: Topics in Reliability Authors: Dana Crowe & Alec Feinberg 8. Reliability Statistics Simplified 8.1 Introduction 8.2 Definitions and Reliability Mathematics 8.3 Failure Rate Concepts 8.4 Reliability Models 8.5 Reliability Objectives and Confidence Testing 8.6 Parametric and Catastrophic Methods 8.7 Influence of Acceleration Factors on Test Planning References Appendix A – AT&T and Common Weibull Model Comparisons Appendix B – Helpful Microsoft® Excel Functions 9. Concepts in Accelerated Testing 9.1 Introduction 9.2 Common Sense Guidelines for Preventing Anomalous Accelerated Testing Failures 9.3 Time Acceleration Factor 9.4 Applications to Accelerated Testing 9.5 High-Temperature Operating Life Acceleration Model 9.6 Temperature-Humidity-Bias Acceleration Model 9.7 Temperature Cycle Acceleration Model 9.8 Vibration Acceleration Model 9.9 Electromigration Acceleration Model 9.10 Failure-Free Accelerated Test Planning 9.11 Step-Stress Testing 9.12 Describing Life Distributions as a Function of Stress 9.13 Summary References10. Accelerated Reliability Growth 10.1 Introduction 10.2 Estimating Benefits with Reliability Growth Fixes 10.3 Accelerated Reliability Growth Methodology 10.4 Applying Accelerated Reliability Growth Theory 10.5 Assessing Reliability Growth 10.6 Summary References Appendix – Accelerated Reliability Growth Stage Gate Model 11. Reliability Predictive Modeling 11.1 Introduction 11.2 System Reliability Modeling 11.3 Customer Expectations 11.4 Various Methods 11.5 Common Problems References Appendix A – Tabulated k of n System Effective Failure Rates Appendix B – Redundancy Equation with and without Repair Appendix C – Availability 12. Failure Modes and Effects Analysis 12.1 Failure Modes and Effects Analysis 12.2 FMEA Goal and Vision 12.3 FMEA Concepts 12.4 Types of FMEA Evaluations 12.5 Objectives 12.6 An FMEA Example 12.7 Implementation Methods Appendix A – Guide to Assigning FMEA Key Criteria Appendix B – FMEA Forms 13. Evaluating Product Risk 13.1 Introduction 13.2 Goals of a Risk Program 13.3 Managing Risks for Your Program 13.4 Four Steps to Risk Management 13.5 Guidelines for Risk Planning (Step 1) 13.6 Guidelines for Risk Assessment (Step 2) 13.7 Guidelines for Risk Analysis (Step 3) 13.8 Guidelines for Risk Handling (Step 4) 14. Thermodynamic Reliability Engineering 14.1 Thermodynamics and Reliability Engineering 14.2 The System and Its Environment 14.3 The Aging Process 14.4 Aging Due to Cyclic Force 14.5 Corrosion and Activation 14.6 Diffusion 14.7 Transistor Aging of Key Device Parameters 14.8 Understanding Logarithmic-in-Time Parametric Aging Associated with Activated Processes 14.9 Summary References
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