HDLBits练习-Building Larger Circuits

HDLBits练习

Circuits-Building Larger Circuits

题1:Counter with period 1000

module top_module (
    input clk,
    input reset,
    output [9:0] q);
	always@(posedge clk)begin
        if(reset)
            q<=10'd0;
        else
            q<=(q==10'd999)? 10'd0 : q+1'd1;
    end
endmodule

题2：4-bit shift register and down counter

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    always@(posedge clk)begin
        case({shift_ena,count_ena})
            2'b10: q<={q[2:0],data};
            2'b01: q<=q-1'd1;
            default:q<=q;
        endcase
    end
endmodule

题3：FSM: Sequence 1101 recognizer

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
reg [2:0]state,next_state;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;
always@(posedge clk)begin
    if(reset)begin
        state<=s0;
    end
    else begin
        state<=next_state;
    end
end
always@(*)begin
    case(state)
    s0:next_state=(data==1)? s1 : s0;
    s1:next_state=(data==1)? s2 : s0;
    s2:next_state=(data==1)? s2 : s3;
    s3:next_state=(data==1)? s4 : s0;
    s4:next_state=s4;
    endcase
end
assign start_shifting=(state==s4);
endmodule

题4：FSM: Enable shift register

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    reg [2:0]count;
	always@(posedge clk)begin
        if(reset)begin
            count<=3'd0;
        end
        else begin
            count<=(count==3'd4)? 3'd4 : count+1'd1;
        end
    end
    assign shift_ena=(count!=3'd4);
endmodule

题5：FSM: The complete FSM

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    parameter ini=0,s0=1,s1=2,s2=3,s3=4;
    reg [2:0]state,next_state;
    always@(posedge clk)begin
        if(reset)begin
            state<=ini;
        end
        else begin
            state<=next_state;
        end
    end
    always@(*)begin
        case(state)
        ini:next_state=(data)? s0 : ini;
        s0: next_state=(data)? s1 : ini;
        s1: next_state=(data)? s1 : s2;
        s2: next_state=(data)? s3 : ini;
        s3: next_state=(done && ack)? ini: s3;
        endcase
    end
    
    reg [2:0]ena_c;
    always@(posedge clk)begin
        if(reset | (done && ack))begin
            ena_c<=3'd0;
        end
        else begin
            if(next_state==s3)begin
                ena_c<=(ena_c==3'd7)?3'd7 : ena_c+1'd1;
            end
            else begin
                ena_c<=3'd0;
            end
        end
    end
    assign shift_ena=(ena_c>3'd0 && ena_c<3'd5);

    reg [2:0]s_counting,sn_counting;
    always@(posedge clk)begin
        if(reset)begin
            s_counting<=ini;
        end
        else begin
            s_counting<=sn_counting;
        end
    end
    always@(*)begin
        case(s_counting)
        ini:sn_counting=(ena_c>=3'd4)? s0 :ini;
        s0: sn_counting=(done_counting)?s1:s0;
        s1: sn_counting=(ack)? ini : s1;
        endcase
    end
    assign counting=(s_counting==s0);

    reg [2:0]s_done,sn_done;
    always@(posedge clk)begin
        if(reset)begin
            s_done<=ini;
        end
        else begin
            s_done<=sn_done;
        end
    end
    always@(*)begin
        case(s_done)
        ini:sn_done=(counting && done_counting)? s0 : ini;
        s0: sn_done=(ack)? ini : s0;
        endcase
    end
    assign done=(s_done==s0);

endmodule

题6：The complete timer

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    parameter ini=0,s0=1,s1=2,s2=3,s3=4;
    reg [2:0]state,next_state;
    always @(posedge clk) begin
        if(reset)begin
            state<=ini;         
        end
        else begin
            state<=next_state;
        end
    end
    always@(*)begin
        case(state)
        ini: next_state=(data)? s0 : ini;
        s0:  next_state=(data)? s1 : ini;
        s1:  next_state=(data)? s1 : s2;
        s2:  next_state=(data)? s3 : ini;
        s3:  next_state=(done && ack)? ini : s3;
        endcase
    end
    
    reg [13:0]c;
    always @(posedge clk) begin
        if(reset)begin
            c<=14'd0;
        end
        else begin
            if(next_state==s3)begin
                c<=c+1'd1;
            end
            else begin
                c<=14'd0;
            end
        end
    end

    reg [3:0]delay;
    always@(posedge clk)begin
        if(reset)begin
            delay<=4'd0;
        end
        else begin
            if(c>14'd0 && c<=14'd4)begin
                delay={delay[2:0],data};
            end
            else begin
                if(done && ack)begin
                    delay=4'd0;
                end
                else begin
                    delay=delay;
                end
            end
        end
    end

    wire [13:0]numcounting;
    assign numcounting=(c>14'd4)?(delay+1'd1)*10'd1000 : 14'd0;
    
    reg [2:0]s_counting,sn_counting;
    always@(posedge clk)begin
        if(reset)begin
            s_counting<=ini;
        end
        else begin
            s_counting<=sn_counting;
        end
    end
    always@(*)begin
        case(s_counting)
        ini: sn_counting=(c>=14'd4 && c<=(numcounting+14'd4))? s0 : ini;
        s0:  sn_counting=(c>=(numcounting+14'd4))? s1 : s0;
        s1:  sn_counting=(done && ack)? ini : s1;
        endcase
    end
    assign counting=(s_counting==s0);

    always @(*) begin
        if(c>=14'd4 && c<=14'd15004)begin
            if(14'd4<=c && c<=14'd1004)begin
                count=delay;
            end
            else if(c<=14'd2004)begin
                count=delay-4'd1;
            end
            else if(c<=14'd3004)begin
                count=delay-4'd2;
            end
            else if(c<=14'd4004)begin
                count=delay-4'd3;
            end
            else if(c<=14'd5004)begin
                count=delay-4'd4;
            end
            else if(c<=14'd6004)begin
                count=delay-4'd5;
            end
            else if(c<=14'd7004)begin
                count=delay-4'd6;
            end
            else if(c<=14'd8004)begin
                count=delay-4'd7;
            end
            else if(c<=14'd9004)begin
                count=delay-4'd8;
            end
            else if(c<=14'd10004)begin
                count=delay-4'd9;
            end
            else if(c<=14'd11004)begin
                count=delay-4'd10;
            end
            else if(c<=14'd12004)begin
                count=delay-4'd11;
            end
            else if(c<=14'd13004)begin
                count=delay-4'd12;
            end
            else if(c<=14'd14004)begin
                count=delay-4'd13;
            end
            else begin
                count=delay-4'd14;
            end
        end
        else begin
            count=4'd0;
        end
    end

    reg [2:0]s_done,sn_done;
    always @(posedge clk) begin
        if(reset)begin
            s_done<=ini;
        end
        else begin
            s_done<=sn_done;
        end
    end
    always @(*) begin
        case(s_done)
        ini: sn_done<=(c>14'd4 && c>=(numcounting+14'd4))? s0 : ini;
        s0 : sn_done<=(ack)? ini : s0;
        endcase
    end
    assign done=(s_done==s0);

endmodule

题7：FSM: One-hot logic equations

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //

    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;

    // assign B3_next = ...;
    // assign S_next = ...;
    // etc.
    assign B3_next=state[B2];
    assign S_next=(~d & state[S]) | (~d & state[S1]) | (~d & state[S110]) | (ack & state[Wait]);
    assign S1_next=d & state[S];
    assign Count_next=state[B3] | (state[Count] & !done_counting );
    assign Wait_next=(done_counting & state[Count]) | (~ack & state[Wait]);
    assign done=state[Wait];
    assign counting=state[Count];
    assign shift_ena=state[B0] | state[B1] | state[B2] | state[B3];
endmodule