阻塞式与非阻塞式的区别仿真

阻塞式源代码：

module block(
	//input 
	clk,
	rst_n,
	//output 
	result_o,
	a,
	b 
);
input clk,rst_n;

output reg [4:0] result_o;
output reg [3:0] a,b;
always @(posedge clk )
	begin 
		if(!rst_n)
			begin
				a = 4'd0;
				b = 4'd0;
			end 
		else 
			begin 
				a = 4'd2;
				b = b + 1'b1;
				result_o = a + b + 1'b1;
			end 
	end 

endmodule

阻塞式测试代码：

`timescale 1 ns/ 1 ns
module block_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire [3:0]  a;
wire [3:0]  b;
wire [4:0]  result_o;
parameter CLK_PERIOD = 20;
// assign statements (if any)                          
block i1 (
// port map - connection between master ports and signals/registers   
	.a(a),
	.b(b),
	.clk(clk),
	.result_o(result_o),
	.rst_n(rst_n)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
	clk = 1'b0;
	rst_n = 1'b0;
	#(CLK_PERIOD*5) rst_n = 1'b1;
	#(CLK_PERIOD*5) $stop;
// --> end                                             
$display("Running testbench");                       
end  

always  #(CLK_PERIOD/2) clk = ~clk; 
                                                            
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                          
@eachvec;                                              
// --> end                                             
end                                                    
endmodule

阻塞式仿真波形：

非阻塞式代码：

module block_un(
	//input 
	clk,
	rst_n,
	//output 
	result_o,
	a,
	b 
);
input clk,rst_n;

output reg [4:0] result_o;
output reg [3:0] a,b;
always @(posedge clk )
	begin 
		if(!rst_n)
			begin
				a <= 4'd0;
				b <= 4'd0;
			end 
		else 
			begin 
				a <= 4'd2;
				b <= b + 1'b1;
				result_o <= a + b + 1'b1;
			end 
	end 

endmodule

非阻塞式测试代码：

`timescale 1 ns/ 1 ns
module block_un_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire [3:0]  a;
wire [3:0]  b;
wire [4:0]  result_o;

// assign statements (if any)                          
block_un i1 (
// port map - connection between master ports and signals/registers   
	.a(a),
	.b(b),
	.clk(clk),
	.result_o(result_o),
	.rst_n(rst_n)
);
parameter CLK_PERIOD = 20;
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
 	clk = 1'b0;
	rst_n = 1'b0;
	#(CLK_PERIOD*5) rst_n = 1'b1;
	#(CLK_PERIOD*5) $stop;
// --> end                                             
$display("Running testbench");                       
end  

always  #(CLK_PERIOD/2) clk = ~clk;                                                 
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule

非阻塞式仿真波形：