FPGA学习笔记7--阻塞和非阻塞赋值仿真

阻塞赋值`
module zuse(c,b,a,clk);

 output c,b; 

 input clk,a; 

 reg c,b; 

 always @(posedge clk) 

      begin 

      b=a; 

      c=b; 

      end 

 endmodule 

仿真timescale 1ns/1ns
module tb_zuse();
reg clk;
reg a;
wire c;
wire b;
zuse u1(.a(a),.clk(clk),.b(b),.c©);
initial begin
clk<=1’b0;
a<=1’b0;
#50 a<=1’b1;
#150 $finish;
end
always # 5 clk<=~clk;
endmodule

非阻塞

     module nozuse(c,b,a,clk); 

     output c,b; 

     input clk,a; 

     reg c,b; 

     always @(posedge clk) 

          begin 

          b<=a; 

          c<=b; 

          end 

     endmodule 

`timescale 1ns/1ns
module tb_nozuse();
reg clk;
reg a;
wire c;
wire b;
nozuse u1(.a(a),.clk(clk),.b(b),.c(c));
initial begin
clk<=1'b0;
a<=1'b0;
#55 a<=1'b1;
#150 $finish;
end
always # 5 clk<=~clk;
endmodule