Verilog HDL：PCM解码器设计（Testbench4）

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已于 2023-03-19 21:23:17 修改

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分类专栏： RTL级电路设计文章标签： fpga开发

于 2023-02-01 11:28:45 首次发布

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这是一个用Verilog编写的PCM解码器测试平台，用于测试PCM_DECODER模块。测试脚本生成了SOF（帧起始）、2字节数据（如3C和4D）以及EOF（帧结束）信号，模拟PCM数据流。通过改变din信号的值，模拟不同的数据序列，并使用$fsdb进行波形调试。

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PCM_DECODER_TEST_4.v

/********************************************************************************* 
  *Copyright(C), IC Design
  *FileName: PCM_DECODER_TEST_4.v
  *Author: Yue Shipeng
  *Version: 6.0
  *Date: 2023.01.21 03:00
  *Description: TESTBENCH FOR PCM_DECODER
  *History: Notepad++ version
**********************************************************************************/  

/********************************************************************************* 
PCM DECODER TEST 4
**********************************************************************************/

`timescale 10ns/1ns

module PCM_DECODER_TEST_4;

reg clk;
reg rst;
reg din;
wire [7:0] dout;
wire D_en;
wire F_en;

parameter half_cycle = 10;

PCM_DECODER ut4(
	.clk(clk),
	.rst(rst),
	.din(din),
	.dout(dout),
	.D_en(D_en),
	.F_en(F_en)
);

initial begin
	clk = 0;
	forever begin
		clk = # half_cycle ~ clk;
	end
end

initial begin
	rst = 1;
	# (1 * half_cycle) rst = 0;
	# (2 * half_cycle) rst = 1;
end

initial begin

	// the initial set of din;
	din <= 0;
	
	// the SOF generation;
	repeat (4) @ (posedge clk);
	din <= 1;
	repeat (16) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (160) @ (posedge clk);
	din <= 1;
	
	// the 2 Byte data generation;
	
	// 3C, 0011_1100;
	wave_00();
	wave_11();
	wave_11();
	wave_00();
	
	// 4D, 0100_1101;
	wave_01();
	wave_11();
	wave_00();
	wave_01();

	// the EOF generation;
	repeat (48) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (32) @ (posedge clk);
	din <= 0;
	
	repeat (20) @ (posedge clk);
	$finish;
end

initial begin
	$fsdbDumpfile("./verdiFsdb/PCM_DECODER_TEST_4.fsdb");
	$fsdbDumpvars(0);
end

// the 00 generation;
task wave_00();
	repeat (16) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (128) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (16) @ (posedge clk);
	din <= 1;
endtask

// the 01 generation;
task wave_01();
	repeat (16) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (96) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (48) @ (posedge clk);
	din <= 1;
endtask

// the 10 generation;
task wave_10();
	repeat (48) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (96) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (16) @ (posedge clk);
	din <= 1;
endtask

// the 11 generation;
task wave_11();
	repeat (48) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (64) @ (posedge clk);
	din <= 0;
	repeat (16) @ (posedge clk);
	din <= 1;
	repeat (48) @ (posedge clk);
	din <= 1;
endtask

endmodule