VHDL四位计数器编写（手把手）

quartus新建工程和仿真操作参考这篇博文，只需修改工程名和VHD文件即可
CNT4.vhd文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;  
use ieee.std_logic_unsigned.all; 

ENTITY CNT4 IS
	PORT(CLK,RST_n:IN STD_LOGIC;
		P:OUT STD_LOGIC_VECTOR (3 downto 0));
END ENTITY CNT4;

ARCHITECTURE ART OF CNT4 IS

SIGNAL tmp :STD_LOGIC_VECTOR (3 downto 0);

	BEGIN
	PROCESS (CLK) IS
		BEGIN
		IF(RST_n='1') THEN
			IF (CLK='1' AND CLK'EVENT) THEN
				--tmp<=unsigned(tmp)+'1';
				tmp<=tmp+1;
			END IF;
		ELSE
			tmp<=(others =>'0');
		END IF;
	P<=tmp;	
	END PROCESS;
END ARCHITECTURE ART;

testbench文件，CNT.vht

-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "05/10/2021 20:16:49"
                                                            
-- Vhdl Test Bench template for design  :  CNT4
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY CNT4_vhd_tst IS
END CNT4_vhd_tst;
ARCHITECTURE CNT4_arch OF CNT4_vhd_tst IS
-- constants
constant ClockPeriod :time :=20 ns;                                                   
-- signals                                                   
SIGNAL CLK : STD_LOGIC;
SIGNAL P : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RST_n : STD_LOGIC;
COMPONENT CNT4
	PORT (
	CLK : IN STD_LOGIC;
	P : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	RST_n : IN STD_LOGIC
	);
END COMPONENT;
BEGIN
	i1 : CNT4
	PORT MAP (
-- list connections between master ports and signals
	CLK => CLK,
	P => P,
	RST_n => RST_n
	);
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations
BEGIN                                                         
        -- code executes for every event on sensitivity list
	RST_n<='0';
	wait for ClockPeriod;
	RST_n<='1';		
WAIT;                                                        
END PROCESS always;
GENERATE_CLOCK:PROCESS
BEGIN
	CLK<='0';
	wait for ClockPeriod/2;
	CLK<='1';
	wait for ClockPeriod/2;	
END PROCESS;                                          
END CNT4_arch;

仿真结果