HDLBits 系列（10）——Building Larger Circuits

目录

3.3  Building Larger Circuits

1 . Counter with period 1000

2. 4-bit shift register and down counter

3. FSM: Sequence 1101 recognizer

4. FSM: Enable shift register

 5. FSM: The complete FSM

6. The complete timer

7. FSM: One-hot logic equations

---

3.3  Building Larger Circuits

1 . Counter with period 1000

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,
    output [9:0] q);
    
    always @(posedge clk)begin
        if(reset) q<=10'd0;
        else if(q=='d999) q<=10'd0;
        else q<=q+1'b1;
    end

endmodule

2. 4-bit shift register and down counter

Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

shift_ena 为1的时候，接收数据往左移， count_ena 为1的时候，数据递减，其他时刻保持不变。不考虑这两个使能信号的优先级，选择case语句。

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output reg[3:0] q);
   
    always @(posedge clk)begin
        case({shift_ena,count_ena})
            2'b00:q<=q;
            2'b01:q<=q-1'b1;
            2'b10:q<={q[2:0],data};
            2'b11:q<=q;
        endcase
    end
    
 endmodule

3. FSM: Sequence 1101 recognizer

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shiftingto 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

序列检测：把状态转移图画出来就好写代码了。

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
    parameter S0=0,S1=1,S2=2,S3=3,S4=4;
    reg [2:0] state,next_state;
    
    always @(*)begin
        case(state)
            S0:begin
                if(data) next_state=S1;
                else next_state=S0;
            end
            S1:begin
                if(data) next_state=S2;
                else next_state=S0;
            end
             S2:begin
                 if(data) next_state=S2;
                else next_state=S3;
            end
             S3:begin
                 if(data) next_state=S4;
                else next_state=S0;
            end
            S4:begin
                next_state=S4;
            end
            default:begin
                next_state=S0;
            end
        endcase
    end
    
    always @(posedge clk)begin
        if(reset) state<=S0;
        else state<=next_state;
    end
    
    
    assign start_shifting=(state==S4);
    /*
    parameter S0=0,S1=1,S2=2,S3=3,S4=4;
    reg [2:0] cs,ns;
    
    always @(*)
        begin
            case (cs)
                S0:ns=data?S1:S0;
                S1:ns=data?S2:S0;
                S2:ns=data?S2:S3;
                S3:ns=data?S4:S0;
                S4:ns=data?S4:S4;
            endcase
        end
    always @(posedge clk)
        begin
            if (reset)
                cs<=S0;
            else
                cs<=ns;
        end
    assign start_shifting= (cs==S4);
    */

endmodule

4. FSM: Enable shift register

As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.

Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).

复位信号有效后，shift_ena拉高持续4个时钟周期，其他时刻拉低。

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    
    reg [2:0]cnt;
    
    always @(posedge clk)begin
        if(reset)begin
            cnt<='d0;
            shift_ena<=1'b1;
        end
        else if(shift_ena==1'b1 && cnt==3'd3)begin
            shift_ena<=1'b0;
            cnt<='d0;
        end
        else begin
            cnt<=cnt+1'b1;
        end
    end
            

endmodule

 5. FSM: The complete FSM

You may wish to do FSM: Enable shift register and FSM: Sequence recognizer first.

We want to create a timer that:

1. is started when a particular pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.

In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.

The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.

After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.

At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The state machine should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.

状态转移图：

 参考时序图：

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    parameter S=0,S1=1,S11=2,S110=3;
    parameter B0=4,B1=5,B2=6,B3=7,COUNT=8,WAIT=9;
    reg [3:0] state,next_state;
    reg [3:0]cnt;
    
    always @(*)begin
        case(state)
            S:begin
                if(data) next_state=S1;
                else next_state=S;
            end
            S1:begin
                if(data) next_state=S11;
                else next_state=S;
            end
            S11:begin
                 if(data) next_state=S11;
                else next_state=S110;
            end
            S110:begin
                if(data) next_state=B0;
                else next_state=S;
            end
           B0:begin  
               next_state=B1;
           end
           B1:begin  
               next_state=B2;
           end
           B2:begin  
               next_state=B3;
           end
           B3:begin  
               next_state=COUNT;
           end
           COUNT:begin
               if(done_counting) next_state=WAIT;
               else next_state=COUNT;
           end
          WAIT:begin
                if(ack)next_state=S;
                else next_state=WAIT;
            end
           default:begin
                next_state=S;
            end
        endcase
    end
   
    always @(posedge clk)begin
        if(reset) state<=S;
        else state<=next_state;
    end
    
    
    assign shift_ena=(state==B0|state==B1|state==B2|state==B3);
    assign counting=(state==COUNT);
    assign done=(state==WAIT);
   

endmodule

6. The complete timer

We want to create a timer with one input that:

1. is started when a particular input pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.

The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].

After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).

At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The circuit should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.

在上题的基础上增加了计数时间数据的接收和计算，并检测计数结束信号触发状态转移。

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    
    parameter S=0,S1=1,S11=2,S110=3;
    parameter B0=4,B1=5,B2=6,B3=7,COUNT=8,WAIT=9;
    reg [3:0] state,next_state;
    reg [3:0] delay;
    reg [13:0]cnt_delay;
    reg          done_counting=0;
   
    //状态机
    always @(*)begin
        case(state)
            S:begin
                if(data) next_state=S1;
                else next_state=S;
            end
            S1:begin
                if(data) next_state=S11;
                else next_state=S;
            end
            S11:begin
                 if(data) next_state=S11;
                else next_state=S110;
            end
            S110:begin
                if(data) next_state=B0;
                else next_state=S;
            end
           B0:begin  
               next_state=B1;
           end
           B1:begin  
               next_state=B2;
           end
           B2:begin  
               next_state=B3;
           end
           B3:begin  
               next_state=COUNT;
           end
           COUNT:begin
               if(done_counting) next_state=WAIT;
               else next_state=COUNT;
           end
          WAIT:begin
                if(ack)next_state=S;
                else next_state=WAIT;
            end
           default:begin
                next_state=S;
            end
        endcase
    end  
    always @(posedge clk)begin
        if(reset) state<=S;
        else state<=next_state;
    end
    
    //延时数据接收并存储
    always@(posedge clk)begin
        if(reset) delay<='d0;
        else begin
            case(state)
                B0:begin
                    delay[3]<=data;
                end
                B1:begin
                    delay[2]<=data;
                end
                B2:begin
                    delay[1]<=data;
                end
                B3:begin
                    delay[0]<=data;
                end
                default:begin
                    delay<=delay;
                end
            endcase
        end
    end
    //done_counting==1'b1的条件
    always @(posedge clk)begin
        if(reset)begin
            cnt_delay<='d0;
        end
        else begin
            case(state)
                COUNT:begin
                    cnt_delay<=cnt_delay+1'b1;
                end
                default:begin
                    cnt_delay<='d0;
                end
            endcase
        end
    end
    assign done_counting = (cnt_delay == (delay + 1) * 1000 - 1);
    
    //out signals
    assign count = delay-cnt_delay/1000;
    assign counting=(state==COUNT);
    assign done=(state==WAIT);
endmodule

7. FSM: One-hot logic equations

Given the following state machine with 3 inputs, 3 outputs, and 10 states:

 Derive next-state logic equations and output logic equations by inspection assuming the following one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) = (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)

Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

Write code that generates the following equations:

• B3_next -- next-state logic for state B1
• S_next
• S1_next
• Count_next
• Wait_next
• done -- output logic
• counting
• shift_ena

根据状态转移的结果进行反推由来过程。

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //

    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;

    assign B3_next =state[B2];
    assign S_next =(~d&&state[S])|(~d&&state[S1])|(~d&&state[S110])|(ack&&state[Wait]);
    assign S1_next=d&&state[S];
    assign Count_next=state[B3]|(state[Count]&&~done_counting);
    assign Wait_next=(state[Count]&&done_counting)|(~ack&&state[Wait]);
    assign done=state[Wait];
    assign counting=state[Count];
    assign shift_ena=state[B0]|state[B1]|state[B2]|state[B3];

endmodule